Commit Graph

17 Commits

Author SHA1 Message Date
Akira Hatanaka e24891251c Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
llvm-svn: 129612
2011-04-15 21:51:11 +00:00
Akira Hatanaka aef55c8801 Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
llvm-svn: 129606
2011-04-15 21:00:26 +00:00
Chris Lattner 0ab5e2cded Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!

llvm-svn: 129558
2011-04-15 05:18:47 +00:00
Bruno Cardoso Lopes ed874eff93 Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira
llvm-svn: 127003
2011-03-04 17:51:39 +00:00
Bruno Cardoso Lopes 67fc18a493 Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some minor tweaks
llvm-svn: 118667
2010-11-10 02:13:22 +00:00
Bruno Cardoso Lopes 9c656fe815 Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka (ahatanaka@mips.com)
llvm-svn: 118447
2010-11-08 21:42:32 +00:00
Chris Lattner 72a364c107 fix emacs language spec's, patch by Edmund Grimley-Evans!
llvm-svn: 111241
2010-08-17 16:20:04 +00:00
Jakob Stoklund Olesen b93331f3be Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

llvm-svn: 100384
2010-04-05 03:10:20 +00:00
Bruno Cardoso Lopes a72a505a80 Added support for fround, fextend and FP_TO_SINT
llvm-svn: 72483
2009-05-27 17:23:44 +00:00
Evan Cheng 977e7be9d4 Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.
llvm-svn: 59953
2008-11-24 07:34:46 +00:00
Bruno Cardoso Lopes f714e25f7e Added new features to represent specific instructions groups
llvm-svn: 54213
2008-07-30 17:01:06 +00:00
Bruno Cardoso Lopes bcc2139ba6 Fixed features usage.
llvm-svn: 53277
2008-07-09 05:32:22 +00:00
Bruno Cardoso Lopes c9c3f49993 Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
  yet, but they allow the future inclusion of features easier. Among new features,
  we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
  integer
  and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
  aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
  sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
  FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
  FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
  return copy, no homing location within EABI, non 32-bit stack objects
  arguments, and asm constraint for float.

llvm-svn: 53146
2008-07-05 19:05:21 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Bruno Cardoso Lopes 87bb032c05 Better processor definition
llvm-svn: 43749
2007-11-06 03:15:20 +00:00
Bruno Cardoso Lopes f3c55807f2 support for Schedule included on Mips.td
llvm-svn: 41159
2007-08-18 02:18:07 +00:00
Bruno Cardoso Lopes 35e43c49b0 Initial Mips support, here we go! =)
- Modifications from the last patch included
  (issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.

llvm-svn: 37461
2007-06-06 07:42:06 +00:00