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4 Commits

Author SHA1 Message Date
Matt Arsenault 3661e90e71 AMDGPU: Don't fold subregister extracts into tied operands 
llvm-svn: 278676
 2016-08-15 16:18:36 +00:00
Matt Arsenault 9c47dd583a AMDGPU: Remove some old intrinsic uses from tests 
llvm-svn: 260493
 2016-02-11 06:02:01 +00:00
Matt Arsenault e4d0c142e8 AMDGPU: Add sdst operand to VOP2b instructions 
The VOP3 encoding of these allows any SGPR pair for the i1
output, but this was forced before to always use vcc.
This doesn't yet try to use this, but does add the operand
to the definitions so the main change is adding vcc to the
output of the VOP2 encoding.

llvm-svn: 246358
 2015-08-29 07:16:50 +00:00
Tom Stellard 45bb48ea19 R600 -> AMDGPU rename 
llvm-svn: 239657
 2015-06-13 03:28:10 +00:00