Commit Graph

292721 Commits

Author SHA1 Message Date
Craig Topper 03523f6741 [X86] Regroup some isel patterns. NFC
For some reason the 64-bit patterns were separated from their 8/16/32-bit friends, but only for add/sub/mul. For and/or/xor they were together.

llvm-svn: 335429
2018-06-24 06:56:49 +00:00
Craig Topper 19772c89c7 [X86] Rename VFPCLASSSS and VFPCLASSSD internal instruction names to include a Z to match other EVEX instructions.
llvm-svn: 335428
2018-06-24 06:29:50 +00:00
Zachary Turner aa202f03f7 Also forward declare BitScanReverse.
With the removal of intrin.h in an earlier patch, the intrinsics
that we were actually using were manually re-declared, however
several of them were missed leading to compilation failures with
MSVC.  Fix those.

llvm-svn: 335427
2018-06-24 01:48:25 +00:00
Brad Smith 8c17d5921d Add OpenBSD support to the Threading code
llvm-svn: 335426
2018-06-23 22:02:59 +00:00
Brad Smith 3baae56a03 [CMake] Do not use --gc-sections on OpenBSD
llvm-svn: 335425
2018-06-23 21:43:27 +00:00
Brad Smith ee0e66026b [CMake] Support building shared library for OpenBSD
llvm-svn: 335424
2018-06-23 21:26:44 +00:00
Jonas Devlieghere 77fa07264a [llc] Fix sanitizer failure.
Store the string on the stack rather than just the StringRef.

Fix sanitizer bots:

  http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/19948
  http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-msan/builds/5500

llvm-svn: 335423
2018-06-23 19:04:10 +00:00
Brian Gesiak 12728474b3 [Coroutines] Less IR for noexcept await_resume
Summary:
In his review of https://reviews.llvm.org/D45860, @GorNishanov suggested
avoiding generating additional exception-handling IR in the case that
the resume function was marked as 'noexcept', and exceptions could not
occur. This implements that suggestion.

Test Plan: `check-clang`

Reviewers: GorNishanov, EricWF

Reviewed By: GorNishanov

Subscribers: cfe-commits, GorNishanov

Differential Revision: https://reviews.llvm.org/D47673

llvm-svn: 335422
2018-06-23 18:57:26 +00:00
Duncan P. N. Exon Smith f4c82cffc6 ADT: Use EBO to shrink SmallVector size 1
SmallVectorStorage is empty when its size is 1; use inheritance so that
the empty base class optimization kicks in.

llvm-svn: 335421
2018-06-23 18:39:44 +00:00
Brian Gesiak c1b173a636 [Sema] isValidCoroutineContext FIXME and citations
Summary:
Add citations to the Coroutines TS to the `isValidCoroutineContext`
function, as well as a FIXME and test for [expr.await]p2, which states
a co_await expression cannot be used in a default argument.

Test Plan: check-clang

Reviewers: GorNishanov, EricWF

Reviewed By: GorNishanov

Subscribers: rsmith, cfe-commits

Differential Revision: https://reviews.llvm.org/D48519

llvm-svn: 335420
2018-06-23 18:01:02 +00:00
Reid Kleckner e7a7a5057b Attempt to fix latent tablegen dependency issue
llvm-svn: 335419
2018-06-23 17:32:51 +00:00
Jonas Devlieghere 7762484459 [llc] Use WithColor for printing errors/warnings
Use the WithColor helper from support to print errors and warnings.

llvm-svn: 335418
2018-06-23 16:51:10 +00:00
Jonas Devlieghere 7513a1bf5a [llvm-config] Use WithColor for printing errors.
Use the WithColor helper from support to print errors.

llvm-svn: 335417
2018-06-23 16:50:09 +00:00
Jonas Devlieghere fb54074112 [llvm-mt] Use WithColor for printing errors.
Use the WithColor helper from support to print errors.

llvm-svn: 335416
2018-06-23 16:49:07 +00:00
Jonas Devlieghere c02bf01f64 [TableGen] Use WithColor for printing errors/warnings
Use the WithColor helper from support to print errors and warnings.

llvm-svn: 335415
2018-06-23 16:48:03 +00:00
Craig Topper d8d64a56b5 [X86] Make %eiz usage in 64-bit mode, force a 0x67 address size prefix. Fix some test CHECK lines.
llvm-svn: 335414
2018-06-23 06:15:04 +00:00
Craig Topper 2545529034 [X86] Teach disassembler to use %eip instead of %rip when 0x67 prefix is used on a rip-relative address.
llvm-svn: 335413
2018-06-23 06:03:48 +00:00
Craig Topper 68d64e3859 [X86][AsmParser] Improve base/index register checks.
-Ensure EIP isn't used with an index reigster.
-Ensure EIP isn't used as index register.
-Ensure base register isn't a vector register.
-Ensure eiz/riz usage matches the size of their base register.

llvm-svn: 335412
2018-06-23 05:53:00 +00:00
Stanislav Mekhanoshin d8c9374797 Fix invariant fdiv hoisting in LICM
FDiv is replaced with multiplication by reciprocal and invariant
reciprocal is hoisted out of the loop, while multiplication remains
even if invariant.

Switch checks for all invariant operands and only invariant
denominator to fix the issue.

Differential Revision: https://reviews.llvm.org/D48447

llvm-svn: 335411
2018-06-23 04:01:28 +00:00
Petr Hosek 96917d7912 [Fuchsia] Enable static libc++, libc++abi, libunwind
This is needed for building Fuchsia drivers.

Differential Revision: https://reviews.llvm.org/D48208

llvm-svn: 335410
2018-06-23 03:15:07 +00:00
Reid Kleckner fd7c9ab971 [AMDGPU] Update includes for intrinsic changes :(
llvm-svn: 335409
2018-06-23 03:05:39 +00:00
Lang Hames d716a26e8b [ORC] Fix formatting and list pending queries in VSO::dump.
llvm-svn: 335408
2018-06-23 02:22:10 +00:00
Reid Kleckner f5890e4e43 [IR] Split Intrinsics.inc into enums and implementations
Implements PR34259

Intrinsics.h is a very popular header. Most LLVM TUs care about things
like dbg_value, but they don't care how they are implemented. After I
split these out, IntrinsicImpl.inc is 1.7 MB, so this saves each LLVM TU
from scanning 1.7 MB of source that gets pre-processed away.

It also means we can modify intrinsic properties without triggering a
full rebuild, but that's probably less of a win.

I think the next best thing to do would be to split out the target
intrinsics into their own header. Very, very few TUs care about
target-specific intrinsics. It's very hard to split up the target
independent intrinsics like llvm.expect, assume, and dbg.value, though.

llvm-svn: 335407
2018-06-23 02:02:38 +00:00
Reid Kleckner 5c25346912 Avoid including intrin.h from MathExtras.h
This is repeatably worth 0.3s compile time on MathExtras.cpp. This is a
very popular header, and it basically pulls all Intel intrinsics into
every LLVM TU. Let's not do that.

llvm-svn: 335406
2018-06-23 01:19:49 +00:00
Fangrui Song 4ef42a83f9 [ELF] Change isSectionData to exclude SHF_EXECINSTR
Summary:
This affects what sections are displayed as "DATA" in llvm-objdump.
The other user llvm-size is unaffected.

Before, a "TEXT" section is also "DATA", which seems weird.
The sh_flags condition matches that of bfd's SEC_DATA but the sh_type
condition uses (== SHF_PROGBITS) instead of bfd's (!= SHT_NOBITS).
bfd's SEC_DATA is not appealing as so many sections will be shown as DATA.

Reviewers: jyknight, Bigcheese

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D48472

llvm-svn: 335405
2018-06-23 00:15:33 +00:00
Fangrui Song e737e75491 [ELF] Change llvm-objdump output for D48472: TEXT DATA -> TEXT
Reviewers: jyknight, Bigcheese, espindola

Subscribers: emaste, arichardson, llvm-commits

Differential Revision: https://reviews.llvm.org/D48473

llvm-svn: 335404
2018-06-23 00:15:23 +00:00
Craig Topper abdbb2c67a [X86][AsmParser] Rework that allows (%dx) to be used in place of %dx with in/out instructions.
Previously, to support (%dx) we left a wide open hole in our 16-bit memory address checking. This let this address value be used with any instruction without error in the parser. It would later fail in the encoder with an assertion failure on debug builds and who knows what on release builds.

This patch passes the mnemonic down to the memory operand parsing function so we can allow the (%dx) form only on specific instructions.

llvm-svn: 335403
2018-06-23 00:03:20 +00:00
Reid Kleckner 330f65b3e8 [RuntimeDyld] Implement the ELF PIC large code model relocations
Prerequisite for https://reviews.llvm.org/D47211 which improves our ELF
large PIC codegen.

llvm-svn: 335402
2018-06-22 23:53:22 +00:00
Greg Clayton ef115de629 Update cmdtemplate.py to use best pratices.
Fixes include:
- fix all lint errors
- add code that will automatically register and LLDB command classes by detecting the classes and any classes that have a "register_lldb_command" function
  - automatically fill in the correct module name when registering commands
  - automatically fill in the class name when registering command

llvm-svn: 335401
2018-06-22 23:34:24 +00:00
Eli Friedman 203eaaf5ba [LoopReroll] Rewrite induction variable rewriting.
This gets rid of a bunch of weird special cases; instead, just use SCEV
rewriting for everything.  In addition to being simpler, this fixes a
bug where we would use the wrong stride in certain edge cases.

The one bit I'm not quite sure about is the trip count handling,
specifically the FIXME about overflow.  In general, I think we need to
widen the exit condition, but that's probably not profitable if the new
type isn't legal, so we probably need a check somewhere.  That said, I
don't think I'm making the existing problem any worse.

As a followup to this, a bunch of IV-related code in root-finding could
be cleaned up; with SCEV-based rewriting, there isn't any reason to
assume a loop will have exactly one or two PHI nodes.

Differential Revision: https://reviews.llvm.org/D45191

llvm-svn: 335400
2018-06-22 22:58:55 +00:00
George Burgess IV 2cbf9730b0 [MSSA] Remove incorrect comment + `auto`ify dyn_cast results; NFC
llvm-svn: 335399
2018-06-22 22:34:07 +00:00
Craig Topper 10e2f73793 [X86][AsmParser] Keep track of whether an explicit scale was specified while parsing an address in Intel syntax. Use it for improved error checking.
This allows us to check these:
-16-bit addressing doesn't support scale so we should error if we find one there.
-Multiplying ESP/RSP by a scale even if the scale is 1 should be an error because ESP/RSP can't be an index.

llvm-svn: 335398
2018-06-22 22:28:39 +00:00
Fangrui Song 1e2d5cb06c [llvm-size] Make global variables static
llvm-svn: 335397
2018-06-22 22:20:10 +00:00
Sanjay Patel 80b85a46db [x86] add more tests for bit hacking opportunities with setcc; NFC
Missed cases where the input and output are the same size in rL335391.

llvm-svn: 335396
2018-06-22 22:07:26 +00:00
Sanjay Patel 0fe8ea568b [PowerPC] add more tests for bit hacking opportunities with setcc; NFC
Missed cases where the input and output are the same size in rL335390.

llvm-svn: 335395
2018-06-22 22:06:33 +00:00
Craig Topper 1d707539e4 [X86][AsmParser] In Intel syntax make sure we support ESP/RSP being the second register in memory expressions like [EAX+ESP].
By default, the second register gets assigned to the index register slot. But ESP can't be an index register so we need to swap it with the other register.

There's still a slight bug that we allow [EAX+ESP*1]. The existence of the multiply even though its with 1 should force ESP to the index register and trigger an error, but it doesn't currently.

llvm-svn: 335394
2018-06-22 21:57:24 +00:00
JF Bastien ec7d7f312e [Sema] -Wformat-pedantic only for NSInteger/NSUInteger %zu/%zi on Darwin
Summary:
Pick D42933 back up, and make NSInteger/NSUInteger with %zu/%zi specifiers on Darwin warn only in pedantic mode. The default -Wformat recently started warning for the following code because of the added support for analysis for the '%zi' specifier.

     NSInteger i = NSIntegerMax;
     NSLog(@"max NSInteger = %zi", i);

The problem is that on armv7 %zi is 'long', and NSInteger is typedefed to 'int' in Foundation. We should avoid this warning as it's inconvenient to our users: it's target specific (happens only on armv7 and not arm64), and breaks their existing code. We should also silence the warning for the '%zu' specifier to ensure consistency. This is acceptable because Darwin guarantees that, despite the unfortunate choice of typedef, sizeof(size_t) == sizeof(NS[U]Integer), the warning is therefore noisy for pedantic reasons. Once this is in I'll update public documentation.

Related discussion on cfe-dev:
http://lists.llvm.org/pipermail/cfe-dev/2018-May/058050.html

<rdar://36874921&40501559>

Reviewers: ahatanak, vsapsai, alexshap, aaron.ballman, javed.absar, jfb, rjmccall

Subscribers: kristof.beyls, aheejin, cfe-commits

Differential Revision: https://reviews.llvm.org/D47290

llvm-svn: 335393
2018-06-22 21:54:40 +00:00
Matt Davis eb7488e799 [llvm-mca] Remove unnecessary include and forward decl in RCU. NFC.
The DispatchUnit is no longer a dependency of RCU, so this patch removes a
stale include and forward decl.  This patch also cleans up some comments.

llvm-svn: 335392
2018-06-22 21:35:26 +00:00
Sanjay Patel 705cde3ac8 [x86] add tests for bit hacking opportunities with setcc; NFC
We likely gave up on folding some select-of-constants patterns in 
IR with rL331486, and we need to recover those in the DAG.

The tests without select are based on our current DAGCombiner 
optimizations for select-of-constants.

llvm-svn: 335391
2018-06-22 21:16:54 +00:00
Sanjay Patel 6e505e4388 [PowerPC] add tests for bit hacking opportunities with setcc; NFC
We likely gave up on folding some select-of-constants patterns in 
IR with rL331486, and we need to recover those in the DAG.

The tests without select are based on our current DAGCombiner 
optimizations for select-of-constants.

llvm-svn: 335390
2018-06-22 21:16:29 +00:00
Craig Topper a55cc4a2e9 [X86] Add test cases showing missed select simplifcation for MCU when icmp is in a slightly different form.
These test cases show that the "(select (and (x , 0x1) == 0), y, (z ^ y) ) -> (-(and (x , 0x1)) & z ) ^ y" doesn't work if the select condition is changed to (and (x, 0x1) != 1)

llvm-svn: 335389
2018-06-22 21:09:31 +00:00
Aditya Nandakumar e2a7f31064 [GISel]: Add G_ADDRSPACE_CAST Opcode
Added IRTranslator support for addrspacecast.

https://reviews.llvm.org/D48469

reviewed by: volkan

llvm-svn: 335388
2018-06-22 20:58:51 +00:00
Fangrui Song f2b547f85f [gdb] Use Latin-1 to decode StringRef
llvm-svn: 335387
2018-06-22 20:29:42 +00:00
Adrian Prantl 56a196c020 Mark this test as no debuginfo
llvm-svn: 335386
2018-06-22 20:26:53 +00:00
Tobias Edler von Koch 7609cb83e6 Re-land "[LTO] Enable module summary emission by default for regular LTO"
Since we are now producing a summary also for regular LTO builds, we
need to run the NameAnonGlobals pass in those cases as well (the
summary cannot handle anonymous globals).

See https://reviews.llvm.org/D34156 for details on the original change.

This reverts commit 6c9ee4a4a438a8059aacc809b2dd57128fccd6b3.

llvm-svn: 335385
2018-06-22 20:23:21 +00:00
Craig Topper 9bc2c059c3 [X86] Don't accept (%si,%bp) 16-bit address expressions.
The second register is the index register and should only be %si or %di if used with a base register. And in that case the base register should be %bp or %bx.

This makes us compatible with gas.

We do still need to support both orders with Intel syntax which uses [bp+si] and [si+bp]

llvm-svn: 335384
2018-06-22 20:20:38 +00:00
Vedant Kumar c835306ac5 [ubsan] Fix __ubsan_on_report interface definition
Speculative fix for the interface definition of __ubsan_on_report for
the Windows bots:

  http://lab.llvm.org:8011/builders/sanitizer-windows/builds/30528
  lib\ubsan\ubsan_interface.inc(55): error C2065: '__ubsan_on_report':
  undeclared identifier

INTERCEPT_SANITIZER_WEAK_FUNCTION was the wrong macro to use to begin
with because __ubsan_on_report isn't weak. Reading through that macro,
it's still not clear to me why there is an undefined reference, though,
because it appears to define a dummy __ubsan_on_report shim.

llvm-svn: 335383
2018-06-22 20:15:33 +00:00
Benjamin Kramer 9508af351a Reinstate quotes around the path to python that I accidentaly removed in r335330
This broke users with spaces in the path, like C:\Program Files\Python

llvm-svn: 335382
2018-06-22 20:03:32 +00:00
Richard Smith 69bc9aa22f Restore pre-r335182 behavior for naming inherited constructors as
members of dependent contexts.

This permits cases where the names before and after the '::' in a
dependent inherited constructor using-declaration do not match, but
where we can nonetheless tell when parsing the template that a
constructor is being named. Under (open) core language DR 2070, such
cases will probably be ill-formed, but r335182 does not quite give
that result and didn't intend to change this, so restore the old
behavior for now.

llvm-svn: 335381
2018-06-22 19:50:19 +00:00
Sam Clegg 5421b37893 Fix BUILD_SHARED_LIBS=1 build of libclangHandleLLVM
Differential Revision: https://reviews.llvm.org/D48503

llvm-svn: 335380
2018-06-22 19:44:48 +00:00