36d4dec28a
Thumb1 exception handling setjmp
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llvm-svn: 90246
2009-12-01 18:10:36 +00:00
86fc920742
For VLDM/VSTM (Advanced SIMD), set encoding bits Inst{11-8} to 0b1011.
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llvm-svn: 90243
2009-12-01 17:37:06 +00:00
ee536b0ea4
For VMOV (immediate), make some of the encoding bits (cmode and op) unspecified.
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For VMOVv*i[16,32], op bit is don't care, and some cmode bits vary depending on
the immediate values.
Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
llvm-svn: 90173
2009-12-01 00:02:02 +00:00
3ee8bc9b35
Minor whitespace fixes.
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llvm-svn: 90166
2009-11-30 23:33:53 +00:00
6f51309021
Fix a minor inconsistency.
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llvm-svn: 90165
2009-11-30 23:33:37 +00:00
505ddaa4dc
Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable
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for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low. The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.
llvm-svn: 90144
2009-11-30 18:35:03 +00:00
c168a52627
Fix some more ARM unified syntax warnings.
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llvm-svn: 90141
2009-11-30 17:47:19 +00:00
32f8bb9ed4
Added support to allow clients to custom widen. For X86, custom widen vectors for
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divide/remainder since these operations can trap by unroll them and adding undefs
for the resulting vector.
llvm-svn: 90108
2009-11-30 02:42:02 +00:00
58ccf88c36
update and consolidate the load pre notes.
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llvm-svn: 90050
2009-11-29 02:19:52 +00:00
83a4a9868f
add a deadargelim note.
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llvm-svn: 90009
2009-11-27 17:12:30 +00:00
ca9e0e83b3
This testcase is actually only partially redundant, and requires
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the FIXME I added yesterday to be implemented.
llvm-svn: 90008
2009-11-27 16:53:57 +00:00
cc6d29286c
this (and probably several others) are now done.
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llvm-svn: 89982
2009-11-27 00:35:04 +00:00
9bd2136ca3
Teach memdep to phi translate bitcasts. This allows us to compile
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the example in GCC PR16799 to:
LBB1_2: ## %bb1
movl %eax, %eax
subq %rax, %rdi
movq %rdi, (%rcx)
movl (%rdi), %eax
testl %eax, %eax
je LBB1_2
instead of:
LBB1_2: ## %bb1
movl (%rdi), %ecx
subq %rcx, %rdi
movq %rdi, (%rax)
cmpl $0, (%rdi)
je LBB1_2
llvm-svn: 89978
2009-11-26 23:41:07 +00:00
29bc8a91d3
Teach basicaa that x|c == x+c when the c bits of x are clear. This
...
allows us to compile the example in readme.txt into:
LBB1_1: ## %bb
movl 4(%rdx,%rax), %ecx
movl %ecx, %esi
imull (%rdx,%rax), %esi
imull %esi, %ecx
movl %esi, 8(%rdx,%rax)
imull %ecx, %esi
movl %ecx, 12(%rdx,%rax)
movl %esi, 16(%rdx,%rax)
imull %ecx, %esi
movl %esi, 20(%rdx,%rax)
addq $16, %rax
cmpq $4000, %rax
jne LBB1_1
instead of:
LBB1_1:
movl (%rdx,%rax), %ecx
imull 4(%rdx,%rax), %ecx
movl %ecx, 8(%rdx,%rax)
imull 4(%rdx,%rax), %ecx
movl %ecx, 12(%rdx,%rax)
imull 8(%rdx,%rax), %ecx
movl %ecx, 16(%rdx,%rax)
imull 12(%rdx,%rax), %ecx
movl %ecx, 20(%rdx,%rax)
addq $16, %rax
cmpq $4000, %rax
jne LBB1_1
GCC (4.2) doesn't seem to be able to eliminate the loads in this
testcase either, it generates:
L2:
movl (%rdx), %eax
imull 4(%rdx), %eax
movl %eax, 8(%rdx)
imull 4(%rdx), %eax
movl %eax, 12(%rdx)
imull 8(%rdx), %eax
movl %eax, 16(%rdx)
imull 12(%rdx), %eax
movl %eax, 20(%rdx)
addl $4, %ecx
addq $16, %rdx
cmpl $1002, %ecx
jne L2
llvm-svn: 89952
2009-11-26 16:26:43 +00:00
12dacdd359
teach basicaa that A[i] != A[i+1].
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llvm-svn: 89951
2009-11-26 16:18:10 +00:00
8e09ad6f3c
update some notes slightly
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llvm-svn: 89913
2009-11-26 01:51:18 +00:00
8981b3abe5
Rollback changes r89516: Added two SubtargetFeatures::AddFeatures methods, which accept a comma-separated string or already parsed command line parameters as input, and some code re-factoring to use these new methods.
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llvm-svn: 89893
2009-11-25 22:44:18 +00:00
4419301d81
Tail duplicate indirect branches for PowerPC, too.
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With the testcase for pr3120, the "threaded interpreter" runtime decreases
from 1788 to 1413 with this change.
llvm-svn: 89877
2009-11-25 19:57:14 +00:00
4cd30817d3
Avoid some possibly unsafe uses of StringRef::data().
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llvm-svn: 89873
2009-11-25 18:26:09 +00:00
2d9caf9fe5
Use StringRef (again) in DebugInfo interface.
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llvm-svn: 89866
2009-11-25 17:36:49 +00:00
120f729eca
Based on the testcase for pr3120, running on my MacPro with Xeon processors,
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it is definitely profitable to tail duplicate indirect branches for x86.
This is likely to be true to various degrees for all modern x86 processors.
llvm-svn: 89865
2009-11-25 17:27:53 +00:00
2db07581b7
Support PIC loading of constant pool entries
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llvm-svn: 89863
2009-11-25 12:17:58 +00:00
900f2ce31c
Sketch structure for X86 disassembler.
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llvm-svn: 89850
2009-11-25 06:53:08 +00:00
2c6d498ccc
Use endianess dependent offsets for load/store of doubles when
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using two swc/lwc instead of sdc/ldc.
llvm-svn: 89826
2009-11-25 01:05:25 +00:00
e0eb336588
Fix compiler warnings.
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llvm-svn: 89824
2009-11-25 00:58:21 +00:00
fa2741e0d3
Only include in the callee saved regs the sub registers to avoid
...
unnecessary save/restore.
llvm-svn: 89823
2009-11-25 00:47:43 +00:00
dce6f66cf0
Add proper emission of load/store double to stack slots for mips1 targets!
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llvm-svn: 89821
2009-11-25 00:36:00 +00:00
d23ea6a33b
Revert r89803.
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llvm-svn: 89819
2009-11-25 00:31:13 +00:00
d4d40670e8
Refactor target hook for tail duplication as requested by Chris.
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Make tail duplication of indirect branches much more aggressive (for targets
that indicate that it is profitable), based on further experience with
this transformation. I compiled 3 large applications with and without
this more aggressive tail duplication and measured minimal changes in code
size. ("size" on Darwin seems to round the text size up to the nearest
page boundary, so I can only say that any code size increase was less than
one 4k page.) Radar 7421267.
llvm-svn: 89814
2009-11-24 23:35:49 +00:00
5ece8f0a20
Do not store R31 into the caller's link area on PPC.
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This violates the ABI (that area is "reserved"), and
while it is safe if all code is generated with current
compilers, there is some very old code around that uses
that slot for something else, and breaks if it is stored
into. Adjust testcases looking for current behavior.
I've verified that the stack frame size is right in all
testcases, whether it changed or not. 7311323.
llvm-svn: 89811
2009-11-24 22:59:02 +00:00
29c9b709e3
Enable debug info for ppc-darwin.
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llvm-svn: 89803
2009-11-24 21:38:54 +00:00
184ec26fcd
Enable predication of NEON instructions in Thumb2 mode.
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llvm-svn: 89748
2009-11-24 08:06:15 +00:00
86dcae106d
Make capitalization of names starting "is" more consistent.
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No functional change.
llvm-svn: 89724
2009-11-24 01:09:07 +00:00
ece825dc4f
Data type suffix must come after predicate.
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llvm-svn: 89723
2009-11-24 01:05:23 +00:00
2522908653
Materialize global addresses via movt/movw pair, this is always better
...
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
llvm-svn: 89720
2009-11-24 00:44:37 +00:00
f890f51666
80 column violations
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llvm-svn: 89718
2009-11-24 00:20:27 +00:00
f2ad571443
* Move stub allocation inside the JITEmitter, instead of exposing a
...
way for each TargetJITInfo subclass to allocate its own stubs. This
means stubs aren't as exactly-sized anymore, but it lets us get rid of
TargetJITInfo::emitFunctionStubAtAddr(), which lets ARM and PPC
support the eager JIT, fixing http://llvm.org/PR4816 .
* Rename the JITEmitter's stub creation functions to describe the kind
of stub they create. So far, all of them create lazy-compilation
stubs, but they sometimes get used when far-call stubs are needed.
Fixing http://llvm.org/PR5201 will involve fixing this.
llvm-svn: 89715
2009-11-23 23:35:19 +00:00
de5dea869f
Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
...
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
llvm-svn: 89711
2009-11-23 23:20:51 +00:00
19b48370fb
Allow more than one stub to be being generated at the same time.
...
It's probably better in the long run to replace the
indirect-GlobalVariable system. That'll be done after a subsequent
patch.
llvm-svn: 89708
2009-11-23 22:49:00 +00:00
738a97a1db
Massive refactoring of NEON instructions. Separate opcode from data size specifier suffix, move \t up stream to instruction format, and fix more 80 column violations.
...
This fixes the NEON asm printing so the "predicate" field is printed between the opcode and the data type suffix.
llvm-svn: 89706
2009-11-23 21:57:23 +00:00
dbb4140f37
move fconst[sd] to UAL. <rdar://7414913>
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llvm-svn: 89700
2009-11-23 21:08:25 +00:00
b6528d3244
Partially revert r84730 by removing N2VDup from ARMInstrFormats.td and modifying
...
VDUPLND and VDUPLNQ to derive from N2V instead of N2VDup. VDUPLND and VDUPLNQ
now expect op19_18 and op17_16 as the first two args.
llvm-svn: 89699
2009-11-23 21:00:43 +00:00
04c0e76772
fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate.
...
llvm-svn: 89694
2009-11-23 20:35:53 +00:00
5ad7416260
Revert r84572 by removing N3VImm from ARMInstrFormats.td now that we can specify
...
{?,?,?,?} as op11_8 for VEXTd and VEXTq.
llvm-svn: 89693
2009-11-23 20:09:13 +00:00
e97457afbc
Partially revert r89377 by removing NLdStLN class definition from
...
ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt
instead of NLdStLN.
llvm-svn: 89684
2009-11-23 18:16:16 +00:00
ebc60ef80c
Make it clear that the index bit(s) of Vector Get Lane and Vector Set Lane
...
should be left unspecified now that Bob Wilson has fixed pr5470.
llvm-svn: 89676
2009-11-23 17:48:17 +00:00
1f2457f8aa
Minor itinerary fixes for FP instructions.
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llvm-svn: 89672
2009-11-23 17:34:12 +00:00
fd963e11f5
Move default FrameReg val to getFrameIndexReference(). Otherwise, debug info can get bogus values.
...
llvm-svn: 89618
2009-11-22 20:05:32 +00:00
90e9062e96
Generate more correct debug info for frame indices.
...
llvm-svn: 89576
2009-11-22 02:32:29 +00:00
abdf86d2be
Minor optimization: when doing eq/ne comparions and RHS is a constant - swap operands, this will allow us to fold imm into comparison.
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llvm-svn: 89574
2009-11-22 01:14:08 +00:00
Jim Grosbach