2 Commits

Author	SHA1	Message	Date
Hsiangkai Wang	6e360460f1	[RISCV] Use v8-v23 as argument registers to conform to the proposal. ... The maximum LMUL is 8. We need 16 vector registers for two LMUL-8 arguments. The modification follows the proposal of psABI in https://github.com/riscv/riscv-elf-psabi-doc/pull/171 Differential Revision: https://reviews.llvm.org/D95134	2021-01-22 07:55:24 +08:00
Fraser Cormack	1d4411e9ea	[RISCV] Add vector integer min/max ISel patterns ... Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D94012	2021-01-05 09:15:50 +00:00