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4 Commits

Author SHA1 Message Date
Hsiangkai Wang 6e360460f1 [RISCV] Use v8-v23 as argument registers to conform to the proposal. 
The maximum LMUL is 8. We need 16 vector registers for two LMUL-8
arguments. The modification follows the proposal of psABI in
https://github.com/riscv/riscv-elf-psabi-doc/pull/171

Differential Revision: https://reviews.llvm.org/D95134
 2021-01-22 07:55:24 +08:00
Monk Chiang ecc38eac76 Add intrinsic testcase for some missing widening reduction. 
Add vfredosum/vfredsum/vwredsum/vwredsumu testcase.

Differential Revision: https://reviews.llvm.org/D93887
 2020-12-31 11:15:15 +08:00
Craig Topper 253dc16f9e [RISCV] Cleanup some V intrinsic names used in tests to match the type overloads used. Add some missing double tests on rv32. NFC 
The matching for intrinsic names is forgiving about types in the
name being absent or wrong. Once the intrinsic is parsed its
name will remangled to include the real types.

This commit fixes the names to have at least enough correct types
so that the name used in the test is a prefix of the canonical name.
The big missing part is the type for the VL parameter which changes
size between rv32 and rv64.

While I was in here I noticed that we were missing some tests for
double on rv32 so I fixed that by copying from rv64 and fixing up
the VL argument type.
 2020-12-30 12:37:11 -08:00
Monk Chiang 622ea9cf74 [RISCV] Define vector widening reduction intrinsic. 
Define vwredsumu/vwredsum/vfwredosum/vfwredsum

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Differential Revision: https://reviews.llvm.org/D93807
 2020-12-26 21:42:30 +08:00