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Commit Graph

Author	SHA1	Message	Date
Hsiangkai Wang	aa8d33a6d6	[RISCV] Spilling for Zvlsseg registers. For Zvlsseg, we create several tuple register classes. When spilling for these tuple register classes, we need to iterate NF times to load/store these tuple registers. Differential Revision: https://reviews.llvm.org/D98629	2021-03-19 07:46:16 +08:00

Author

SHA1

Message

Date

Hsiangkai Wang

aa8d33a6d6

[RISCV] Spilling for Zvlsseg registers.

For Zvlsseg, we create several tuple register classes. When spilling for
these tuple register classes, we need to iterate NF times to load/store
these tuple registers.

Differential Revision: https://reviews.llvm.org/D98629

2021-03-19 07:46:16 +08:00

1 Commits