5ca98c657d
Kill info update bugs.
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llvm-svn: 41043
2007-08-13 07:12:23 +00:00
af21e9550e
No need to remove dead range from soon-to-be-dead live interval. Its val# may be out of whack.
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llvm-svn: 41024
2007-08-12 01:26:19 +00:00
05cc486c7b
Code to maintain kill information during register coalescing.
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llvm-svn: 41016
2007-08-11 00:59:19 +00:00
e081928f49
Move isSubRegOf into MRegisterInfo. Fix a missed move elimination in LowerSubregs and add more debugging output there.
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llvm-svn: 41005
2007-08-10 21:11:55 +00:00
a17799a3bd
Fix EXTRACT_ELEMENT, EXTRACT_SUBVECTOR, and EXTRACT_VECTOR_ELT to
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use an intptr ValueType instead of i32 for the index operand in
getCopyToParts.
llvm-svn: 40987
2007-08-10 14:59:38 +00:00
66011c17d5
propagate struct size and alignment of byval arguments to the DAG
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llvm-svn: 40986
2007-08-10 14:44:42 +00:00
2b9fe84b07
unbreak the build
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llvm-svn: 40976
2007-08-09 23:55:17 +00:00
1115a2b412
Bug fix. ~1U marks the val# dead.
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llvm-svn: 40975
2007-08-09 23:14:39 +00:00
c339e45274
Update per review comments.
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llvm-svn: 40965
2007-08-09 17:27:48 +00:00
ba1a98a4e0
long double 9 of N. This finishes up the X86-32 bits
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(constants are still not handled). Adds ConvertActions
to control fp-to-fp conversions (these are currently
defaulted for all other targets, so no changes there).
llvm-svn: 40958
2007-08-09 01:04:01 +00:00
9d09c5ccda
If a target really needs to custom lower constants, it should be allowed
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to do so.
llvm-svn: 40955
2007-08-08 23:23:31 +00:00
d771b793fe
Adding kill info to val#.
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llvm-svn: 40925
2007-08-08 07:03:29 +00:00
103947125c
Clean up and bug fix.
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llvm-svn: 40921
2007-08-08 05:56:18 +00:00
a8c2f38617
- Each val# can have multiple kills.
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- Fix some minor bugs related to special markers on val# def. ~0U means
undefined, ~1U means dead val#.
llvm-svn: 40916
2007-08-08 03:00:28 +00:00
c236617ea0
Remove a dead assertion.
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llvm-svn: 40914
2007-08-08 01:00:21 +00:00
0d0fee269a
- LiveInterval value#'s now have 3 components: def instruction #,
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kill instruction #, and source register number (iff the value# is defined by a
copy).
- Now def instruction # is set for every value#, not just for copy defined ones.
- Update some outdated code related inactive live ranges.
- Kill info not yet set. That's next patch.
llvm-svn: 40913
2007-08-07 23:49:57 +00:00
99905f16f8
Add a missing forward declaration.
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llvm-svn: 40896
2007-08-07 16:34:05 +00:00
079ebcfae5
Fix a regression compiling 2005-05-11-Popcount-ffs-fls with the CBE,
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introduced by chandler's patch.
llvm-svn: 40864
2007-08-06 16:36:18 +00:00
2e5fb9f71e
Implement review feedback. No functionality change.
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llvm-svn: 40863
2007-08-06 16:33:56 +00:00
446282ae3d
Fix minor doxygen nits.
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llvm-svn: 40854
2007-08-05 20:06:04 +00:00
6299a45277
shorten this name
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llvm-svn: 40843
2007-08-05 18:45:33 +00:00
7132e00de7
This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future.
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This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.
llvm-svn: 40807
2007-08-04 01:51:18 +00:00
5f6a9da530
More explicit keywords.
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llvm-svn: 40757
2007-08-02 21:21:54 +00:00
3ffe7187db
don't redefine a parameter
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llvm-svn: 40748
2007-08-02 18:08:16 +00:00
358c3d1dac
Do not emit copies for physical register output if it's not used.
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llvm-svn: 40722
2007-08-02 05:29:38 +00:00
5b80ecbcf5
Style police: Expand the tabs to spaces!
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llvm-svn: 40712
2007-08-02 02:22:46 +00:00
c5549fc3a0
Instead of adding copyfromreg's to handle physical definitions. Now isel can
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simply specify them as results and let scheduledag handle them. That
is, instead of
SDOperand Flag = DAG.getTargetNode(Opc, MVT::i32, MVT::Flag, ...)
SDOperand Result = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, Flag)
Just write:
SDOperand Result = DAG.getTargetNode(Opc, MVT::i32, MVT::i32, ...)
And let scheduledag emit the move from X86::EAX to a virtual register.
llvm-svn: 40710
2007-08-02 00:28:15 +00:00
d8ded48468
Bugs: missing partial uses and redundant partial defs.
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llvm-svn: 40688
2007-08-01 20:18:21 +00:00
0db4418a5f
Expand unaligned loads/stores when the target doesn't support them. (PR1548)
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llvm-svn: 40682
2007-08-01 19:34:21 +00:00
17a5dfe6f7
New CallInst interface to address GLIBCXX_DEBUG errors caused by
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indexing an empty std::vector.
Updates to all clients.
llvm-svn: 40660
2007-08-01 03:43:44 +00:00
e02b2d7e69
simpleregistercoalescing -> regcoalescing. It's too long for me to handle.
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llvm-svn: 40654
2007-07-31 22:37:44 +00:00
34e2d22d63
- Allow custom lowering for CTPOP, CTTZ, CTLZ.
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- Fixed an existing unexpanded tab.
llvm-svn: 40605
2007-07-30 21:00:31 +00:00
4ff9fb14f6
Fix a bug in getCopyFromParts turned up in the testcase for PR1132.
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llvm-svn: 40598
2007-07-30 19:09:17 +00:00
33d0ea2597
Print a space between the comment character and the basic block name,
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for prettiness.
llvm-svn: 40593
2007-07-30 15:06:25 +00:00
644f917358
Support for trampolines, except for X86 codegen which is
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still under discussion.
llvm-svn: 40549
2007-07-27 12:58:54 +00:00
14bbb15f07
Move subreg lowering pass to be right after regalloc, per feedback.
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llvm-svn: 40548
2007-07-27 07:36:14 +00:00
30f060be80
Fix the alias analysis query in DAGCombiner to not add in two
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offsets. The SrcValueOffset values are the real offsets from the
SrcValue base pointers.
llvm-svn: 40534
2007-07-26 16:14:06 +00:00
e9d738cefc
Add a MachineFunction pass, which runs post register allocation, that turns subreg insert/extract instruction into register copies. This ensures correct code gen if the coalescer isn't able to remove all subreg instructions.
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llvm-svn: 40521
2007-07-26 08:18:32 +00:00
18603b03e1
Teach DAG scheduling how to properly emit subreg insert/extract machine instructions. PR1350
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llvm-svn: 40520
2007-07-26 08:12:07 +00:00
a8fc0e527b
Add selection DAG nodes for subreg insert/extract. PR1350
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llvm-svn: 40516
2007-07-26 07:34:40 +00:00
0dbc152d2e
Remove subreg index from MachineInstr's and also keep vregs as unsigned when adding operands.
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llvm-svn: 40514
2007-07-26 07:00:46 +00:00
3fead96121
Fix infinite recursion for when extract_vector_elt is legal. Unfortunately no public targets use this code-path, so no test.
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llvm-svn: 40510
2007-07-26 03:33:13 +00:00
86eb3fd97d
EmitAlignment() also emits optional fill value.
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llvm-svn: 40500
2007-07-25 23:35:07 +00:00
64b64ae591
Minor cleanup:
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- Split EH and debug infiormation
- Make DwarfWriter more verbose in some cases
llvm-svn: 40481
2007-07-25 00:06:28 +00:00
f0bb12848f
Add const to CanBeFoldedBy, CheckAndMask, and CheckOrMask.
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llvm-svn: 40480
2007-07-24 23:00:27 +00:00
b6a8ae20c7
Fix some uses of dyn_cast to be uses of cast.
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llvm-svn: 40443
2007-07-23 20:24:29 +00:00
147d9fa57d
Don't assume that only Uses can be kills. Defs are marked as kills initially
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when there are no uses. This fixes a dangling-pointer bug, where pointers to
deleted instructions were not removed from kills lists. More info here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2007-July/009749.html
llvm-svn: 40131
2007-07-20 23:17:34 +00:00
9d5df0a5f6
Added -print-emitted-asm to print out JIT generated asm to cerr.
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llvm-svn: 40123
2007-07-20 21:56:13 +00:00
85ec2af554
As pointed out by g++-4.2, the original code didn't do
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what it thought it was doing.
llvm-svn: 40044
2007-07-19 07:31:58 +00:00
a8d152a22a
Add comment.
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llvm-svn: 40022
2007-07-18 23:34:48 +00:00
Evan Cheng