2 Commits

Author	SHA1	Message	Date
Matt Arsenault	74fd7600d2	AMDGPU: Handle partial shift reduction for variable shifts ... If the variable shift amount has known bits, we can still reduce the shift. llvm-svn: 331917	2018-05-09 20:52:54 +00:00
Matt Arsenault	b143d9a5ea	AMDGPU: Partially shrink 64-bit shifts if reduced to 16-bit ... This is an extension of an existing combine to reduce wider shls if the result fits in the final result type. This introduces the same combine, but reduces the shift to a middle sized type to avoid the slow 64-bit shift. llvm-svn: 331916	2018-05-09 20:52:43 +00:00