846bcff7c7
Assembly parsing for 4-register variant of VLD1.
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llvm-svn: 142682
2011-10-21 20:35:01 +00:00
c4360fe575
Assembly parsing for 3-register variant of VLD1.
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llvm-svn: 142675
2011-10-21 20:02:19 +00:00
2f2e3c4737
ARM VLD parsing and encoding.
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Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
llvm-svn: 142670
2011-10-21 18:54:25 +00:00
12a16dbcb0
Ensure timestamps are not embedded into files when doing a release build.
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llvm-svn: 142647
2011-10-21 09:47:14 +00:00
7e9a7c4a7f
Modify the script to output the regressions and passes into categories. My Python-fu could use some improving...
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llvm-svn: 142643
2011-10-21 06:58:01 +00:00
d1bb644171
Check for divide by zero.
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llvm-svn: 142640
2011-10-21 06:26:01 +00:00
f105192ad5
Also compare the built dragonegg objects between phases 2 and 3.
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llvm-svn: 142608
2011-10-20 20:14:18 +00:00
9341b50c07
Reset the system compiler each time we start a new flavour. Otherwise
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the last compiler built for the previous flavour is used for the next,
for example the Debug clang compiler was being used for the initial build
of the Release LLVM. Flavors should be independent of each other. This
especially matters if the compiler built for the previous flavour doesn't
actually work!
llvm-svn: 142607
2011-10-20 20:10:58 +00:00
2efb4dd0cb
Add support for testing dragonegg. This is disabled by default.
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In fact this commit is not intended to change anything unless you
use one of the new command line flags.
llvm-svn: 142577
2011-10-20 11:13:04 +00:00
6966b4c2b2
Revamp the script to handle the 'TEST=simple' output.
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llvm-svn: 142559
2011-10-20 00:45:46 +00:00
a96c00bf47
Duncan pointed out that sometimes CC and CXX are used to specify the compiler. Also that the configure script takes care of finding an appropriate compiler if one's not specified.
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llvm-svn: 142489
2011-10-19 09:47:00 +00:00
f96a5bc15b
Use bash instead.
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llvm-svn: 142486
2011-10-19 09:25:49 +00:00
cfe8232d23
Make changes so that this runs on FreeBSD.
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llvm-svn: 142482
2011-10-19 08:42:07 +00:00
c39977d01b
Adding dependencies to allow -DBUILD_SHARED_LIBS=true to complete.
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llvm-svn: 142464
2011-10-19 00:13:13 +00:00
ad47cfcef9
ARM VTBL (one register) assembly parsing and encoding.
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llvm-svn: 142441
2011-10-18 23:02:30 +00:00
06ac75c8e3
Don't exit just because some early commands fail. Use the -k flag when running the checks.
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llvm-svn: 142369
2011-10-18 17:27:12 +00:00
e4454e0de2
ARM assembly parsing and encoding for VMOV.i64.
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llvm-svn: 142356
2011-10-18 16:18:11 +00:00
8211c051ca
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
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llvm-svn: 142321
2011-10-18 00:22:00 +00:00
cda32ae372
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
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llvm-svn: 142303
2011-10-17 23:09:09 +00:00
741cd73aab
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
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NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
llvm-svn: 142293
2011-10-17 22:26:03 +00:00
a5748e22e2
Forgot to add the project name to the 'svn ls' command.
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llvm-svn: 142282
2011-10-17 21:45:07 +00:00
6bf79084c3
Add message to svn mkdir command.
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llvm-svn: 142280
2011-10-17 21:42:29 +00:00
b7d9ee707d
Fix unused variable warning in the rare circumstance that we have no feature-dependent instructions.
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llvm-svn: 142193
2011-10-17 16:56:47 +00:00
77dfde0ba3
Pick low-hanging MatchEntry shrinkage fruit.
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Shaves 200k off Release-Asserts clang binaries on i386.
llvm-svn: 142191
2011-10-17 16:18:09 +00:00
f95c94e9a6
Don't download and compile compiler-rt, libcxx, and libcxxabi by default.
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llvm-svn: 142185
2011-10-17 08:41:20 +00:00
7b7d077c29
Update to disable asserts. Build a phase 3 compiler, and compare phase 2 files against phase 3.
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llvm-svn: 142173
2011-10-17 04:46:54 +00:00
9aa3943d9e
Overhaul the 'test-release' script.
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This removes support for building llvm-gcc. It will eventually add support for
building other projects.
llvm-svn: 142165
2011-10-16 22:44:08 +00:00
ef22c60abd
Update the tree before applying patch.
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llvm-svn: 142155
2011-10-16 20:59:25 +00:00
96fa597828
Add X86 PEXTR and PDEP instructions.
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llvm-svn: 142141
2011-10-16 16:50:08 +00:00
aea148c366
Add X86 BZHI instruction as well as BMI2 feature detection.
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llvm-svn: 142122
2011-10-16 07:55:05 +00:00
0ae8d4d738
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
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llvm-svn: 142117
2011-10-16 07:05:40 +00:00
03b80a4027
Make SMDiagnostic a little more sane. Instead of passing around note/warning/error as a
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string, pass it around as an enum.
llvm-svn: 142107
2011-10-16 05:43:57 +00:00
a3a0681083
Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance
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the X86 asmparser to produce ranges in the one case that was annoying me, for example:
test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
^~~~~~~
It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use
ranges where appropriate if someone is interested.
llvm-svn: 142106
2011-10-16 04:47:35 +00:00
25ea4e5ad3
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
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llvm-svn: 142105
2011-10-16 03:51:13 +00:00
6b8fe982e0
Add a helper script to create branches and tag release candidates.
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llvm-svn: 142098
2011-10-16 02:03:18 +00:00
90f98e704d
Add a script that helps merge changes into a release branch.
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llvm-svn: 142097
2011-10-16 01:54:03 +00:00
27ad12539d
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
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llvm-svn: 142082
2011-10-15 20:46:47 +00:00
1dafb035c6
Fix threads/jobs Calculation
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Pass the correct jobs and threads information to the builder.
We were underutilizing the number of jobs and threads specified
by the user.
llvm-svn: 141977
2011-10-14 19:12:37 +00:00
327c643ec2
Add Helpful Messages
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Bit just a bit more verbose about what's going on. Print options
to make to aid debugging.
llvm-svn: 141976
2011-10-14 19:12:35 +00:00
0907a61acb
Add Option to Skip Install
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Add a --no-install option to skip installing components. This
speeds up the develop/test cycle.
llvm-svn: 141975
2011-10-14 19:12:34 +00:00
d42442d646
Add Option to Skip gcc Build
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And a --no-gcc option to skip dragonegg and gcc builds.
This greatly speeds up the develop/test cycle.
llvm-svn: 141974
2011-10-14 19:12:33 +00:00
965de2c197
Add X86 ANDN instruction. Including instruction selection.
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llvm-svn: 141947
2011-10-14 07:06:56 +00:00
d9444d455e
Ban rematerializable instructions with side effects.
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TableGen infers unmodeled side effects on instructions without a
pattern. Fix some instruction definitions where that was overlooked.
Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.
llvm-svn: 141929
2011-10-14 01:00:49 +00:00
483995875f
ARM parsing and encoding for the <option> form of LDC/STC instructions.
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llvm-svn: 141786
2011-10-12 17:34:41 +00:00
6878b1f233
Remove extra semicolon.
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llvm-svn: 141699
2011-10-11 19:53:40 +00:00
a697852386
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
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llvm-svn: 141642
2011-10-11 04:34:23 +00:00
a1ac0dab2d
Emit full ED initializers even for pseudo-instructions.
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This should unbreak the picky buildbots.
llvm-svn: 141575
2011-10-10 20:15:49 +00:00
b253f490c3
Insert dummy ED table entries for pseudo-instructions.
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The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.
Add a test case for xorps which has a very high opcode that exposes this
problem.
llvm-svn: 141562
2011-10-10 18:30:16 +00:00
d0637bfc68
ARM NEON assembly parsing and encoding for VDUP(scalar).
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llvm-svn: 141446
2011-10-07 23:56:00 +00:00
33f619971f
Remove Multidefs
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Multidefs are a bit unwieldy and incomplete. Remove them in favor of
another mechanism, probably for loops.
Revert "Make Test More Thorough"
Revert "Fix a typo."
Revert "Vim Support for Multidefs"
Revert "Emacs Support for Multidefs"
Revert "Document Multidefs"
Revert "Add a Multidef Test"
Revert "Update Test for Multidefs"
Revert "Process Multidefs"
Revert "Parser Multidef Support"
Revert "Lexer Support for Multidefs"
Revert "Add Multidef Data Structures"
llvm-svn: 141378
2011-10-07 18:25:05 +00:00
Jim Grosbach