Commit Graph

1065 Commits

Author SHA1 Message Date
Craig Topper 66e588be09 Add ops() method to SDNode that returns an ArrayRef<SDUse>. Use it to simplify some code.
llvm-svn: 211993
2014-06-29 00:40:57 +00:00
Matt Arsenault d782d05666 R600: Move trivial getters into header, use initializer list
llvm-svn: 211917
2014-06-27 17:57:00 +00:00
Matt Arsenault 642d2e78b3 R600: Don't crash on unhandled instruction in promote alloca
llvm-svn: 211906
2014-06-27 16:52:49 +00:00
Matt Arsenault 6f62cf80d0 Fix missing newline and simplify debug printing.
llvm-svn: 211850
2014-06-27 02:36:59 +00:00
Matt Arsenault 961ca43180 R600: Move load/store ReplaceNodeResults to common code.
Future patches will want to custom lower loads on SI.

llvm-svn: 211848
2014-06-27 02:33:47 +00:00
Matt Arsenault 0989d51520 R600/SI: Add FP mode bits to binary.
The default rounding mode to initialize the mode register needs
to be reported to the runtime. Fill in other bits a kernel
may be interested in setting for future use.

llvm-svn: 211791
2014-06-26 17:22:30 +00:00
Aaron Ballman 3c81e46b57 Silencing a warning about isZExtFree hiding an inherited virtual function. No functional change intended.
llvm-svn: 211783
2014-06-26 13:45:47 +00:00
Matt Arsenault c6f8fdb4e5 R600: Fix vector FMA
llvm-svn: 211757
2014-06-26 01:28:05 +00:00
Tom Stellard b02c268cbd R600/SI: Use a ComplexPattern for MUBUF stores
Now that non-leaf ComplexPatterns are allowed we can fold all the MUBUF
store patterns into the instruction definition.  We will also be able to
reuse this new ComplexPattern for MUBUF loads and atomic operations.

llvm-svn: 211644
2014-06-24 23:33:07 +00:00
Tom Stellard 9b3816b5ee R600: Promote i64 stores to v2i32
Now we need only one 64-bit pattern for stores.

llvm-svn: 211643
2014-06-24 23:33:04 +00:00
Matt Arsenault 257d48d22c R600: Fix inconsistency in rsq instructions.
R600 was using a clamped version of rsq, but SI was not. Add a
new rsq_clamped intrinsic and use them consistently.

It's unclear to me from the documentation what behavior
the R600 instructions have, so I assume they have the legacy behavior
described by the SI documents. For R600, use RECIPSQRT_IEEE
for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also
has RECIPSQRT_FF, which I'm not sure how it fits in here.

llvm-svn: 211637
2014-06-24 22:13:39 +00:00
Matt Arsenault d40b970616 R600: Remove DIV_INF
This corresponded to an amdil instruction which there is
a 2 instruction equivalent for.

llvm-svn: 211616
2014-06-24 17:42:16 +00:00
Matt Arsenault bd469d5e67 R600/SI: Move pattern to instruction definition
llvm-svn: 211614
2014-06-24 17:17:06 +00:00
Matt Arsenault becb140324 R600/SI: Verify restrictions on div_scale operands.
llvm-svn: 211524
2014-06-23 18:28:31 +00:00
Matt Arsenault f2b0aebb8a R600/SI: Fix div_scale intrinsic.
The operand that must match one of the others does matter,
and implement selecting for it.

llvm-svn: 211523
2014-06-23 18:28:28 +00:00
Matt Arsenault 1d555c4e91 R600: Remove AMDILISelLowering
llvm-svn: 211519
2014-06-23 18:00:55 +00:00
Matt Arsenault d5f91fd883 R600: Select is not expensive.
llvm-svn: 211518
2014-06-23 18:00:52 +00:00
Matt Arsenault c4d3d3a16e R600: Move add/sub with overflow out of AMDILISelLowering
Add more tests for these.

llvm-svn: 211517
2014-06-23 18:00:49 +00:00
Matt Arsenault e54e1c3a21 R600: Move more out of AMDILISelLowering
llvm-svn: 211516
2014-06-23 18:00:44 +00:00
Matt Arsenault 72573adbf2 R600: Don't set fp_round_inreg action.
There's no point in setting this since it seems to only
by created in 1 place for ppcf128

llvm-svn: 211515
2014-06-23 18:00:41 +00:00
Matt Arsenault b8b5153935 R600/SI: Handle i64 sub.
We can handle it the same way as add

llvm-svn: 211514
2014-06-23 18:00:38 +00:00
Matt Arsenault 9fa3f93173 R600/SI: Move selection of i64 add to separate function.
Also don't use a SmallVector for fixed size array.

llvm-svn: 211513
2014-06-23 18:00:34 +00:00
Matt Arsenault c791f39912 R600: Rename AMDIL file
llvm-svn: 211512
2014-06-23 18:00:31 +00:00
Matt Arsenault f4d871b113 Fix missing words in sentence
llvm-svn: 211511
2014-06-23 18:00:26 +00:00
Matt Arsenault 762ef017db Use helper function
llvm-svn: 211510
2014-06-23 18:00:24 +00:00
Matt Arsenault 236d9afd18 Alphabetize forward declarations
llvm-svn: 211509
2014-06-23 18:00:20 +00:00
Jan Vesely 343cd6f056 R600: Use LowerSDIVREM for i64 node replace
v2: move div/rem node replacement to R600ISelLowering
    make lowerSDIVREM protected

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211478
2014-06-22 21:43:01 +00:00
Jan Vesely 109efdff6a R600: Implement custom SDIVREM.
Instead of separate SDIV/SREM. SDIV used UDIV which in turn used UDIVREM anyway.
SREM used SDIV(UDIV->UDIVREM)+MUL+SUB, using UDIVREM directly is more efficient.

v2: Don't use all caps names

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211477
2014-06-22 21:43:00 +00:00
Tom Stellard ae4c9e7bc3 R600/SI: Add patterns for ctpop inside a branch
llvm-svn: 211378
2014-06-20 17:06:11 +00:00
Tom Stellard 9c603ebca4 R600/SI: Add a pattern for f32 ftrunc
llvm-svn: 211377
2014-06-20 17:06:09 +00:00
Tom Stellard a79e9f0f6d R600: Expand vector flog2
llvm-svn: 211376
2014-06-20 17:06:07 +00:00
Tom Stellard 5222a88653 R600: Expand vector fexp2
llvm-svn: 211375
2014-06-20 17:06:05 +00:00
Tom Stellard de16a2e59f R600/SI: SI Control Flow Annotation bug fixed
Mixing of AddAvailableValue and GetValueAtEndOfBlock methods of SSAUpdater
leaded to the endless loop generation when the nested loops annotated.

This fixes a bug in the OCL_ML/KNN OpenCV test.  The test case is too
complex for FileCheck and would be very fragile.

Patch by: Elena Denisova

llvm-svn: 211374
2014-06-20 17:06:02 +00:00
Tom Stellard c9dedb8e29 R600/SI: Add a VALU pattern for i64 xor
llvm-svn: 211373
2014-06-20 17:05:57 +00:00
Matt Arsenault f5e2997aff R600: Trivial subtarget feature cleanups.
Remove an unused AMDIL leftover, correct extra periods
appearing in the help menu.

llvm-svn: 211341
2014-06-20 06:50:05 +00:00
Alp Toker 1d099d9339 Fix typos
llvm-svn: 211304
2014-06-19 19:41:26 +00:00
Craig Topper 35b2f75733 Convert some assert(0) to llvm_unreachable or fold an 'if' condition into the assert.
llvm-svn: 211254
2014-06-19 06:10:58 +00:00
Matt Arsenault a0050b0961 R600/SI: Add intrinsics for various math instructions.
These will be used for custom lowering and for library
implementations of various math functions, so it's useful
to expose these as builtins.

llvm-svn: 211247
2014-06-19 01:19:19 +00:00
Matt Arsenault 2b0fa433a0 Use stdint macros for specifying size of constants
llvm-svn: 211231
2014-06-18 22:11:03 +00:00
Matt Arsenault 692bd5ec2f R600: Handle fnearbyint
The difference from rint isn't really relevant here,
so treat them as equivalent. OpenCL doesn't have nearbyint,
so this is sort of pointless other than for completeness.

llvm-svn: 211229
2014-06-18 22:03:45 +00:00
Marek Olsak 51b8e7b2e7 R600/SI: add gather4 and getlod intrinsics (v3)
This contains all the previous patches + getlod support on top of it.
It doesn't use SDNodes anymore, so it's quite small.
It also adds v16i8 to SReg_128, which is used for the sampler descriptor.

Reviewed-by: Tom Stellard
llvm-svn: 211228
2014-06-18 22:00:29 +00:00
Matt Arsenault b55c68f171 Use LL suffix for literal that should be 64-bits.
This hopefully fixes Windows

llvm-svn: 211225
2014-06-18 21:40:43 +00:00
Jan Vesely 85f0dbce5c R600: Expand vector fceil
Move fp64 fceil tests to fceil64.ll

v2: rebase

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211194
2014-06-18 17:57:29 +00:00
Matt Arsenault d22626f6bb Work around ridiculous warning.
Apparently C++ doesn't really have hex floating point constants.

llvm-svn: 211192
2014-06-18 17:45:58 +00:00
Matt Arsenault 43160e7af2 R600/SI: Add intrinsics for brev instructions
llvm-svn: 211187
2014-06-18 17:13:57 +00:00
Matt Arsenault dbc9aae1fb R600/SI: Prettier operand printing for 64-bit ops.
Copy what is done for 32-bit already so the order is about the same.

llvm-svn: 211186
2014-06-18 17:13:51 +00:00
Matt Arsenault 4601093267 R600: Implement f64 ftrunc, ffloor and fceil.
CI has instructions for these, so this fixes them for older hardware.

llvm-svn: 211183
2014-06-18 17:05:30 +00:00
Matt Arsenault e8208ec95b R600: Custom lower f64 frint for pre-CI
llvm-svn: 211182
2014-06-18 17:05:26 +00:00
Matt Arsenault 7aeb813b2a R600/SI: Temporary fix for f64 fneg
This should be a source modifier, but this unblocks
most of my math patches.

llvm-svn: 211181
2014-06-18 17:05:22 +00:00
Matt Arsenault 520e7c44c1 R600/SI: Comparisons set vcc.
llvm-svn: 211178
2014-06-18 16:53:48 +00:00
Jan Vesely ecf5133a2b R600: Implement 64bit SRA
v2: Use capitalized variable name

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211159
2014-06-18 12:27:17 +00:00
Jan Vesely 900ff2e74b R600: Implement 64bit SRL
v2: use C++ style comment

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211158
2014-06-18 12:27:15 +00:00
Jan Vesely 25f362766e R600: Implement 64bit SHL
v2: Use c++ style comment

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211157
2014-06-18 12:27:13 +00:00
Tom Stellard 092f332ef2 R600/SI: Make sure target flags are set on pseudo VOP3 instructions
llvm-svn: 211120
2014-06-17 19:34:46 +00:00
Matt Arsenault 295b86e81d R600/SI: Match cttz_zero_undef
llvm-svn: 211116
2014-06-17 17:36:27 +00:00
Matt Arsenault 8579601050 R600/SI: Match ctlz_zero_undef
llvm-svn: 211115
2014-06-17 17:36:24 +00:00
Tom Stellard 880a80ad07 R600: Use LDS and vectors for private memory
llvm-svn: 211110
2014-06-17 16:53:14 +00:00
Tom Stellard 85ad429f1f R600/SI: Add a pattern for llvm.AMDGPU.barrier.global
llvm-svn: 211109
2014-06-17 16:53:09 +00:00
Tom Stellard aad4659470 SelectionDAG: Expand i64 = FP_TO_SINT i32
llvm-svn: 211108
2014-06-17 16:53:07 +00:00
Tom Stellard 8942276a2a R600/SI: Re-initialize the m0 register after using it for indirect addressing
We need to store a value greater than or equal to the number of LDS
bytes allocated by the shader in the m0 register in order for LDS
instructions to work correctly.

We always initialize m0 at the beginning of a shader, but this register
is also used for indirect addressing offsets, so we need to
re-initialize it any time we use indirect addressing.

llvm-svn: 211107
2014-06-17 16:53:04 +00:00
Matt Arsenault 2a60de548a Fix copy paste error
llvm-svn: 211003
2014-06-15 21:22:52 +00:00
Matt Arsenault 717c1d0319 R600: Remove a few more things from AMDILISelLowering
Try to keep all the setOperationActions for integer ops
together.

llvm-svn: 211001
2014-06-15 21:08:58 +00:00
Matt Arsenault b5dff9ab50 R600: Fix assert on vector sdiv
llvm-svn: 211000
2014-06-15 21:08:54 +00:00
Matt Arsenault 14d4645e46 R600: Move / cleanup more leftover AMDIL stuff.
llvm-svn: 210998
2014-06-15 20:23:38 +00:00
Matt Arsenault 1578aa78d4 R600: Move division custom lowering out of AMDILISelLowering
llvm-svn: 210997
2014-06-15 20:08:02 +00:00
Matt Arsenault cf9a9a148e R600: Report that integer division is expensive.
Divides by weird constants now emit much better code.

llvm-svn: 210995
2014-06-15 19:48:16 +00:00
Matt Arsenault 66ee0816da R600: Remove dead code
llvm-svn: 210994
2014-06-15 19:48:13 +00:00
Matt Arsenault b2e8744eeb Fix typo
llvm-svn: 210968
2014-06-14 04:26:07 +00:00
Matt Arsenault e682a19a1c R600: Fix asserts related to constant initializers
This would assert if a constant address space was extern
and therefore didn't have an initializer. If the initializer
was undef, it would hit the unreachable unhandled initializer case.

An extern global should never really occur since we don't have
machine linking, but bugpoint likes to remove initializers.

llvm-svn: 210967
2014-06-14 04:26:05 +00:00
Matt Arsenault 41aa27c96b R600: Use address space enum instead of value
llvm-svn: 210966
2014-06-14 04:26:01 +00:00
Matt Arsenault fd8c24ede8 R600: Cleanup some old AMDIL stuff.
Move / delete some of the more obviously wrong
setOperationAction calls. Most of these are setting Expand
for types that aren't legal which is the default anyway.
Leave stuff that might require more thought on whether it's
junk or not as it is.

No functionality change.

llvm-svn: 210922
2014-06-13 17:20:53 +00:00
Tom Stellard bc5b5370de R600: Remove AMDIL instruction and register definitions
Most of these are no longer used any more.

llvm-svn: 210915
2014-06-13 16:38:59 +00:00
Matt Arsenault c02eea7f64 R600: Don't call setOperationAction with things that aren't opcodes.
CondCode actions are set with setCondCodeAction.
This should have been a harmless bug since the values seem to only
collide only with nodes that don't need to be handled, and these are
already correctly setup elsewhere.

llvm-svn: 210888
2014-06-13 07:44:38 +00:00
Matt Arsenault 825fb0b094 R600/SI: Fix selection error on i64 rotl / rotr.
Evergreen is still broken due to missing shl_parts.

llvm-svn: 210885
2014-06-13 04:00:30 +00:00
Tom Stellard 2e59a45f80 R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget
llvm-svn: 210869
2014-06-13 01:32:00 +00:00
Tom Stellard d881e9195a R600: Drop use of cached TargetMachine in R600InstrInfo.cpp
llvm-svn: 210868
2014-06-13 01:31:56 +00:00
Tom Stellard bfd480d79f R600: Drop use of cached TargetMachine in AMDGPUInstrInfo.cpp
llvm-svn: 210865
2014-06-13 01:02:57 +00:00
Matt Arsenault 5d47d4ac7e R600: Mostly remove remaining AMDIL intrinsics.
Delete all unused ones, and add new AMDGPU named intrinsics for
the ones that are. Handle the old AMDIL names for comptability (although
remove their GCCBuiltin names) and add tests since there weren't any
for these before.

llvm-svn: 210827
2014-06-12 21:15:44 +00:00
Matt Arsenault 2c81994f92 R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*
There is not such thing as a 0-data ds instruction, and the data
operand needs to be a vgpr set to something meaningful.

llvm-svn: 210756
2014-06-12 08:21:54 +00:00
Tom Stellard 4a9cea608c R600: Set correct InstrItinClass for instructions using *Helper classes
We weren't doing this before, so all instruction using the *Helper
classes were considered for any ALU slot.

This fixes a hang in the builtin-char-clz-1.0.generated.cl piglit test.

llvm-svn: 210703
2014-06-11 20:51:42 +00:00
Tom Stellard 3fe21f8afa R600: BCNT_INT is a vector only instruction
llvm-svn: 210702
2014-06-11 20:51:39 +00:00
Matt Arsenault 2acc7a4570 R600/SI: Fix bitcast between v2i32 and f64
This is the same problem fixed in r210664 for more types.

The test passes without this fix. For some reason
I'm only hitting this when creating selects lowered
to v2i32 selects.

llvm-svn: 210692
2014-06-11 19:31:13 +00:00
Matt Arsenault 845438204f R600/SI: Update place using old subtarget predicate
llvm-svn: 210683
2014-06-11 18:11:34 +00:00
Matt Arsenault caa0ec2851 R600/SI: Add common 64-bit LDS atomics
llvm-svn: 210680
2014-06-11 18:08:54 +00:00
Matt Arsenault 1f10c5e2c9 R600/SI: Add instruction definitions for 64-bit LDS atomics
llvm-svn: 210679
2014-06-11 18:08:50 +00:00
Matt Arsenault c793e1d9dc R600/SI: Add 32-bit LDS atomic cmpxchg
llvm-svn: 210678
2014-06-11 18:08:48 +00:00
Matt Arsenault 9e874541ac R600/SI: Use LDS atomic inc / dec
llvm-svn: 210677
2014-06-11 18:08:45 +00:00
Matt Arsenault 0e69e8128c R600/SI: Add other LDS atomic operations
llvm-svn: 210676
2014-06-11 18:08:42 +00:00
Matt Arsenault 8c6613d2bf R600/SI: Add instruction definitions for more LDS ops
llvm-svn: 210675
2014-06-11 18:08:39 +00:00
Matt Arsenault 7ddcd83d49 R600/SI: Fix backwards names for local atomic instructions.
The manual lists them as *_RTN_U32, not *_U32_RTN, which is more
consistent with how every other sized instruction is named.

llvm-svn: 210674
2014-06-11 18:08:37 +00:00
Matt Arsenault 725741004c R600/SI: Refactor local atomics.
Use patterns that will also match the immediate offset to
match the normal read / writes.

llvm-svn: 210673
2014-06-11 18:08:34 +00:00
Matt Arsenault 364a6747aa R600/SI: Use v_cvt_f32_ubyte* instructions
This eliminates extra extract instructions when loading an i8 vector to
a float vector.

llvm-svn: 210666
2014-06-11 17:50:44 +00:00
Matt Arsenault 064c206d23 R600/SI: Fix selection failure on scalar_to_vector
There seem to be only 2 places that produce these,
and it's kind of tricky to hit them.

Also fixes failure to bitcast between i64 and v2f32,
although this for some reason wasn't actually broken in the
simple bitcast testcase, but did in the scalar_to_vector one.

llvm-svn: 210664
2014-06-11 17:40:32 +00:00
Rafael Espindola ace0080a4a Try to fix the msvc build.
llvm-svn: 210636
2014-06-11 04:41:37 +00:00
Matt Arsenault 10da3b2516 Use cast instead of assert + dyn_cast
llvm-svn: 210628
2014-06-11 03:30:06 +00:00
Matt Arsenault c9df794042 R600: Add helper functions.
Extract these from some of my other patches, since this
is the only thing really making them dependent on each other.

llvm-svn: 210627
2014-06-11 03:29:54 +00:00
Tom Stellard 4e07b1d76b R600/SI: Emit an error when attempting to spill VGPRs v4
I can't get VGPR spilling to work reliable, so for now just emit
an error when the register allocator tries to spill VGPRs.

v2:
  - Fix build
v3:
  - Added crash fix when spilling SPGRs
v4:
  - Use V_MOV_B32 as a dummy instruction instead of S_NOP

Patch by: Darren Powell

https://bugs.freedesktop.org/show_bug.cgi?id=75276

llvm-svn: 210588
2014-06-10 21:20:41 +00:00
Tom Stellard 060ae39022 R600/SI: Fix a crash when spilling SGPRs
We need to make sure only one new instruction is added when spilling
otherwise the register allocator may crash.

This fixes a crash in the game Antichamber.

https://bugs.freedesktop.org/show_bug.cgi?id=75276

llvm-svn: 210587
2014-06-10 21:20:38 +00:00
Matt Arsenault 6042506b5c R600: Use BCNT_INT for evergreen
llvm-svn: 210569
2014-06-10 19:18:28 +00:00
Matt Arsenault 8333e4378e R600/SI: Implement i64 ctpop
llvm-svn: 210568
2014-06-10 19:18:24 +00:00