3c7d6eb64c
Cleanup vector logical ops in AVX and add use int versions for simple
...
v2i64
llvm-svn: 137919
2011-08-18 02:11:34 +00:00
a90896397b
Port new Thumb1 encoding tests over to decoding tests.
...
llvm-svn: 137902
2011-08-17 23:37:33 +00:00
1b43828958
ARM assembly parsing and encoding test for BKPT.
...
llvm-svn: 137898
2011-08-17 23:11:13 +00:00
e3bdcd0ea8
ARM assembly parsing and encoding test for BIC.
...
llvm-svn: 137895
2011-08-17 23:00:53 +00:00
cbd4ab104b
Thumb assembly parsing and encoding for B.
...
llvm-svn: 137891
2011-08-17 22:57:40 +00:00
d3e8e29124
Thumb assembly parsing and encoding for ASR.
...
llvm-svn: 137889
2011-08-17 22:49:09 +00:00
9a468153e1
Atomic load/store handling for the passes using memdep (GVN, DSE, memcpyopt).
...
llvm-svn: 137888
2011-08-17 22:22:24 +00:00
1a87fcb9ba
Fix PR10688. Add support for spliting 256-bit vector shifts when the
...
shift amount is variable
llvm-svn: 137885
2011-08-17 22:12:20 +00:00
e2a0404a69
Thumb assembly parsing and encoding for ADR.
...
llvm-svn: 137864
2011-08-17 20:37:40 +00:00
e2d152016f
Add a couple of FIXMEs.
...
llvm-svn: 137861
2011-08-17 20:35:57 +00:00
35ea5cfd46
Fix test case.
...
llvm-svn: 137847
2011-08-17 18:48:28 +00:00
ae2848ed69
Remove superficial test.
...
llvm-svn: 137846
2011-08-17 18:39:13 +00:00
3fee10b7d2
Robustify test.
...
llvm-svn: 137845
2011-08-17 18:38:44 +00:00
d40d838cc4
Start building a Thumb1 decoding test file based on the Thumb1 parsing/encoding test file.
...
llvm-svn: 137840
2011-08-17 18:21:36 +00:00
d7749be2d7
Silly mistake from r137777; restore significant isStructTy() checks. While here, be a bit more defensive
...
with unknown instructions.
Fixes PR10687.
llvm-svn: 137836
2011-08-17 18:10:43 +00:00
80636b48c0
Thumb assembly parsing and encoding for ADC(register) instruction.
...
llvm-svn: 137833
2011-08-17 17:55:28 +00:00
a806eebe13
Add missing '@' delimiter.
...
llvm-svn: 137832
2011-08-17 17:46:01 +00:00
a4043c4b32
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
...
Patch by James Molloy.
llvm-svn: 137830
2011-08-17 17:44:15 +00:00
be5e987379
Introduce matching patterns for vbroadcast AVX instruction. The idea is to
...
match splats in the form (splat (scalar_to_vector (load ...))) whenever
the load can be folded. All the logic and instruction emission is
working but because of PR8156, there are no ways to match loads, cause
they can never be folded for splats. Thus, the tests are XFAILed, but
I've tested and exercised all the logic using a relaxed version for
checking the foldable loads, as if the bug was already fixed. This
should work out of the box once PR8156 gets fixed since MayFoldLoad will
work as expected.
llvm-svn: 137810
2011-08-17 02:29:19 +00:00
3400825b41
Update test to not use the scalar type to splat from a load
...
llvm-svn: 137809
2011-08-17 02:29:15 +00:00
ed786a346e
Now that we have a canonical way to handle 256-bit splats:
...
vinsertf128 $1 + vpermilps $0, remove the old code that used to first
do the splat in a 128-bit vector and then insert it into a larger one.
This is better because the handling code gets simpler and also makes a
better room for the upcoming vbroadcast!
llvm-svn: 137807
2011-08-17 02:29:10 +00:00
5360f88355
Add support for ext and ins.
...
llvm-svn: 137804
2011-08-17 02:05:42 +00:00
e9ab47a72a
Thumb ADD(immediate) parsing support.
...
llvm-svn: 137788
2011-08-16 23:57:34 +00:00
e1df253200
An additional atomic test; related to r137662.
...
llvm-svn: 137786
2011-08-16 23:29:17 +00:00
b7fa2c0a53
Thumb parsing diagnostics for low-reg requirements on ADD and MOV.
...
llvm-svn: 137779
2011-08-16 22:20:01 +00:00
0793eb4c46
A bunch of misc fixes to SCCPSolver::ResolvedUndefsIn, including a fix to stop
...
making random bad assumptions about instructions which are not explicitly listed.
Includes fix for rdar://9956541, a version of "undef ^ undef should return
0 because it's easier than arguing with users".
llvm-svn: 137777
2011-08-16 22:06:31 +00:00
d56ba41bc3
Remove tests that have been obsoleted or migrated to clang/optimizer tests.
...
llvm-svn: 137775
2011-08-16 21:46:25 +00:00
58ffdccab1
Thumb assembly parsing and encoding for ADD(register) instruction.
...
llvm-svn: 137759
2011-08-16 21:34:08 +00:00
56f2f21254
Minor bug in SCCP found by inspection. (I don't think it's possible to hit this with a normal pass pipeline, but fixing for completeness.)
...
llvm-svn: 137755
2011-08-16 21:12:35 +00:00
2c21bf4b43
Add testcase for r137746.
...
llvm-svn: 137754
2011-08-16 21:11:21 +00:00
d3ad0aa413
Tidy up formatting.
...
llvm-svn: 137747
2011-08-16 20:55:41 +00:00
3e941aee69
ARM thumb assembly parsing for arithmetic flag setting instructions.
...
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.
llvm-svn: 137746
2011-08-16 20:45:50 +00:00
2e99f1b3aa
Instead of always leaving the work to the generic legalizer when
...
there is no support for native 256-bit shuffles, be more smart in some
cases, for example, when you can extract specific 128-bit parts and use
regular 128-bit shuffles for them. Example:
For this shuffle:
shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32>
<i32 1, i32 0, i32 7, i32 6>
This was expanded to:
vextractf128 $1, %ymm1, %xmm2
vpextrq $0, %xmm2, %rax
vmovd %rax, %xmm1
vpextrq $1, %xmm2, %rax
vmovd %rax, %xmm2
vpunpcklqdq %xmm1, %xmm2, %xmm1
vpextrq $0, %xmm0, %rax
vmovd %rax, %xmm2
vpextrq $1, %xmm0, %rax
vmovd %rax, %xmm0
vpunpcklqdq %xmm2, %xmm0, %xmm0
vinsertf128 $1, %xmm1, %ymm0, %ymm0
ret
Now we get:
vshufpd $1, %xmm0, %xmm0, %xmm0
vextractf128 $1, %ymm1, %xmm1
vshufpd $1, %xmm1, %xmm1, %xmm1
vinsertf128 $1, %xmm1, %ymm0, %ymm0
llvm-svn: 137733
2011-08-16 18:21:54 +00:00
7d7bec5acf
Add test case for r137711.
...
llvm-svn: 137725
2011-08-16 17:32:01 +00:00
45e50d8a0b
ARM .align NOP padding uses different encoding pre-ARMv6.
...
Patch by Kristof Beyls and James Malloy.
llvm-svn: 137723
2011-08-16 17:06:20 +00:00
2263c10946
Fix handling of double precision loads and stores when Mips1 is targeted.
...
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.
Without the changes made in this patch, llc produces code that has the same
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.
llvm-svn: 137711
2011-08-16 03:51:51 +00:00
ac992afd93
Fix test.
...
llvm-svn: 137703
2011-08-16 01:42:56 +00:00
a917d4f9b4
Revert a bit of r137667; the logic in question can safely handle atomic load/store.
...
llvm-svn: 137702
2011-08-16 01:28:22 +00:00
5403862ab7
Migrate this test from llvm/test/FrontendC++/ptr-to-method-devirt.cpp and
...
FileCheckize. It is more properly an optimizer test.
llvm-svn: 137700
2011-08-16 01:17:17 +00:00
0ffdf2ea0b
Update SimplifyCFG for atomic operations.
...
This commit includes a mention of the landingpad instruction, but it's not
changing the behavior around it. I think the current behavior is correct,
though. Bill, can you double-check that?
llvm-svn: 137691
2011-08-15 23:59:28 +00:00
01a67111d1
Add comments and test for atomic load/store and mem2reg.
...
llvm-svn: 137690
2011-08-15 23:55:52 +00:00
53440984b3
Add a test file for Thumb2 NEON.
...
llvm-svn: 137687
2011-08-15 23:42:20 +00:00
67005029bc
Reorder declarations of vmovmskp* and also put the necessary AVX
...
predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.
llvm-svn: 137684
2011-08-15 23:36:45 +00:00
8bc586e770
Update instcombine for atomic load/store.
...
llvm-svn: 137664
2011-08-15 22:09:40 +00:00
cbe7feeab9
Fix PR10656. It's only profitable to use 128-bit inserts and extracts
...
when AVX mode is one. Otherwise is just more work for the type
legalizer.
llvm-svn: 137661
2011-08-15 21:45:54 +00:00
5286bd2d01
Add some more comprehensive VFP decoding tests.
...
llvm-svn: 137657
2011-08-15 21:29:01 +00:00
8c5f3f7624
Fix this test to avoid leaving a temporary file behind.
...
llvm-svn: 137651
2011-08-15 20:55:03 +00:00
91386c7be4
Atomic load/store support in LICM.
...
llvm-svn: 137648
2011-08-15 20:52:09 +00:00
1d5d2cac8c
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
...
Patch by James Molloy.
llvm-svn: 137647
2011-08-15 20:51:32 +00:00
990dd3d0fb
Add an ipsccp test. Migrated from test/FrontendC++.
...
llvm-svn: 137646
2011-08-15 20:50:36 +00:00
944f4923a4
Add a test for Thumb1 LDRSH decoding.
...
llvm-svn: 137645
2011-08-15 20:15:43 +00:00
f746b0ec53
Add testcase for STRH. Patch by James Molloy.
...
llvm-svn: 137644
2011-08-15 20:12:03 +00:00
61a3ece665
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
...
llvm-svn: 137641
2011-08-15 20:08:25 +00:00
3157f2eebe
Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
...
llvm-svn: 137636
2011-08-15 19:00:06 +00:00
b9d82f411c
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
...
llvm-svn: 137635
2011-08-15 18:44:44 +00:00
746e317953
This transform is not safe. Thanks to Eli for pointing that out!
...
llvm-svn: 137575
2011-08-14 04:51:49 +00:00
ae13df60a6
Don't attempt to add 'nsw' when intermediate instructions had no such guarantee.
...
llvm-svn: 137572
2011-08-14 03:41:33 +00:00
de49278c26
Teach instcombine to preserve the nsw bit by doing an after-the-fact analysis
...
when combining add and sub instructions. Patch by Pranav Bhandarkar!
llvm-svn: 137570
2011-08-14 01:45:19 +00:00
9f56acc124
Fix test.
...
llvm-svn: 137556
2011-08-13 17:06:34 +00:00
d1de7764be
Expand VMOVQQQQ pseudo instructions.
...
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed. Our register allocator must be awesome!
llvm-svn: 137551
2011-08-13 05:14:55 +00:00
02e737b08e
Move "atomic" and "volatile" designations on instructions after the opcode
...
of the instruction.
Note that this change affects the existing non-atomic load and store
instructions; the parser now accepts both forms, and the change is noted
in the release notes.
llvm-svn: 137527
2011-08-12 22:50:01 +00:00
f15dfe5818
The VPERM2F128 is a AVX instruction which permutes between two 256-bit
...
vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.
llvm-svn: 137519
2011-08-12 21:48:26 +00:00
2fcc1cfdce
Define unaligned load and store.
...
llvm-svn: 137515
2011-08-12 21:30:06 +00:00
2d1d7a11f8
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
...
llvm-svn: 137502
2011-08-12 20:36:11 +00:00
ed6d3e813e
Port over the basic ARM encodings test file to a decoding test file. Greatly increases our test coverage of basic ARM-mode instructions.
...
llvm-svn: 137495
2011-08-12 19:42:45 +00:00
2f6b944f56
Test case for 137484
...
llvm-svn: 137486
2011-08-12 18:12:06 +00:00
d1b60f7a6d
Tidy up formatting.
...
llvm-svn: 137471
2011-08-12 17:43:31 +00:00
234317d12a
Tidy up formatting.
...
llvm-svn: 137464
2011-08-12 17:01:02 +00:00
91ea511436
MachOWriter: Don't crash on fixups with arithmetic, emit a relocation instead. This matches what as does.
...
llvm-svn: 137414
2011-08-12 01:51:29 +00:00
10a18d55ce
Don't convert objc_autoreleaseReturnValue to objc_autorelease if the result
...
is returned through a bitcast.
llvm-svn: 137402
2011-08-12 00:36:31 +00:00
121302772d
Don't let arbitrary calls disrupt nested retain+release pairs if
...
the retains and releases all use the same SSA pointer value.
Also, don't let CFG hazards disrupt nested retain+release pair
optimizations.
llvm-svn: 137399
2011-08-12 00:26:31 +00:00
1978ddf769
Clean up formatting a bit.
...
llvm-svn: 137393
2011-08-11 23:57:17 +00:00
8cffa28af8
ARM vector compare to zero instruction assembly parsing support.
...
llvm-svn: 137389
2011-08-11 23:51:13 +00:00
2d8494a030
A slew of unit tests for the recent LoopInfo::updateUnloop feature
...
checked in at r137276 and r137341.
llvm-svn: 137385
2011-08-11 23:38:09 +00:00
2b6860f0a1
Allow loop unrolling to get known trip counts from ScalarEvolution.
...
SCEV unrolling can unroll loops with arbitrary induction variables. It
is a prerequisite for -disable-iv-rewrite performance. It is also
easily handles loops of arbitrary structure including multiple exits
and is generally more robust.
This is under a temporary option to avoid affecting default
behavior for the next couple of weeks. It is needed so that I can
checkin unit tests for updateUnloop.
llvm-svn: 137384
2011-08-11 23:36:16 +00:00
79d60d0e94
Enclose directive .cprestore with .set macro and nomacro to silence assembler
...
warning.
llvm-svn: 137378
2011-08-11 22:42:31 +00:00
aa07cb6a98
Fix tests per now-correct encoding as of r137371.
...
llvm-svn: 137376
2011-08-11 22:31:48 +00:00
e25942154c
ARM STRT assembly parsing and encoding.
...
llvm-svn: 137372
2011-08-11 22:18:00 +00:00
a2b8b60646
ARM load shifted register pre-index fix shift value asm parser encoding.
...
llvm-svn: 137367
2011-08-11 22:05:09 +00:00
8fbf023c9b
Add a dag combine to xform 256-bit shuffles into simple vector
...
inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.
llvm-svn: 137362
2011-08-11 21:50:44 +00:00
9eb3762e08
Fix the test added by Nadav in r137308. Make it more strict:
...
1) check for the "v" version of movaps
2) add a couple of CHECK-NOT to guarantee the behavior
3) move to a more appropriate test file
llvm-svn: 137361
2011-08-11 21:50:35 +00:00
7db3bfbd45
ARM STRHT assembly parsing and encoding.
...
llvm-svn: 137358
2011-08-11 21:39:41 +00:00
d886f8cd8d
ARM STRH assembly parsing and encoding.
...
llvm-svn: 137353
2011-08-11 21:17:22 +00:00
3a850f28d0
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
...
llvm-svn: 137347
2011-08-11 20:47:56 +00:00
887c0b1358
Improve operand validation for Thumb2 addressing modes.
...
llvm-svn: 137344
2011-08-11 20:40:40 +00:00
eb09f49a7f
ARM STRD assembly parsing and encoding.
...
llvm-svn: 137342
2011-08-11 20:28:23 +00:00
6066340301
Continue to tighten decoding by performing more operand validation.
...
llvm-svn: 137340
2011-08-11 20:21:46 +00:00
2a50260f2f
ARM STRBT assembly parsing and encoding.
...
llvm-svn: 137337
2011-08-11 20:04:56 +00:00
d0767f37c1
Add FIXME.
...
llvm-svn: 137336
2011-08-11 19:43:42 +00:00
295788756d
ARM STRB assembly parsing and encoding tests.
...
llvm-svn: 137335
2011-08-11 19:42:58 +00:00
14a4164206
Fix a copy/paste error so that LDRB(register) actually gets tested.
...
llvm-svn: 137333
2011-08-11 19:34:23 +00:00
06b7f0c901
ARM STR(register) assembly parsing and encoding tests.
...
llvm-svn: 137332
2011-08-11 19:26:17 +00:00
d564bf3181
ARM STR(immediate) assembly parsing and encoding.
...
llvm-svn: 137331
2011-08-11 19:22:40 +00:00
3477f2cea5
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
...
llvm-svn: 137325
2011-08-11 19:00:18 +00:00
043c820800
Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict.
...
llvm-svn: 137324
2011-08-11 18:59:13 +00:00
0e15b48f3c
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
...
llvm-svn: 137323
2011-08-11 18:55:42 +00:00
e33c95d39b
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
...
llvm-svn: 137322
2011-08-11 18:41:59 +00:00
ed25385227
Improve error checking in the new ARM disassembler. Patch by James Molloy.
...
llvm-svn: 137320
2011-08-11 18:24:51 +00:00
27ad83d8a9
ARM push of a single register encodes as pre-indexed STR.
...
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
llvm-svn: 137318
2011-08-11 18:07:11 +00:00
8ba76c6d5c
ARM pop of a single register encodes as post-indexed LDR.
...
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
llvm-svn: 137316
2011-08-11 17:35:48 +00:00
1542d5a00a
[AVX] If the data which is going to be saved is already in two XMM registers
...
(for example, after integer operation), do not pack the registers into a YMM
before saving. Its better to save as two XMM registers.
Before:
vinsertf128 $1, %xmm3, %ymm0, %ymm3
vinsertf128 $0, %xmm1, %ymm3, %ymm1
vmovaps %ymm1, 416(%rsp)
After:
vmovaps %xmm3, 416+16(%rsp)
vmovaps %xmm1, 416(%rsp)
llvm-svn: 137308
2011-08-11 16:41:21 +00:00
5a2c70cc8f
add missing colon, thanks peter.
...
llvm-svn: 137306
2011-08-11 16:15:10 +00:00
96710b4308
fix PR10605 / rdar://9930964 by adding a pretty scary missed check.
...
It's somewhat surprising anything works without this. Before we would
compile the testcase into:
test: # @test
movl $4, 8(%rdi)
movl 8(%rdi), %eax
orl %esi, %eax
cmpl $32, %edx
movl %eax, -4(%rsp) # 4-byte Spill
je .LBB0_2
now we produce:
test: # @test
movl 8(%rdi), %eax
movl $4, 8(%rdi)
orl %esi, %eax
cmpl $32, %edx
movl %eax, -4(%rsp) # 4-byte Spill
je .LBB0_2
llvm-svn: 137303
2011-08-11 06:26:54 +00:00
a2d8bb97b9
Splats for v8i32/v8f32 can be handled by VPERMILPSY. This was causing
...
infinite recursive calls in legalize. Fix PR10562
llvm-svn: 137296
2011-08-11 02:49:44 +00:00
572c9aaf53
Use the splat index to generate the desired shuffle. Otherwise we
...
could only get undefs and the vector shuffle becomes an undef,
generating wrong code.
llvm-svn: 137295
2011-08-11 02:49:41 +00:00
3ae39f8ad1
Fix X86TargetLowering::LowerExternalSymbol so that it actually works in non-trivial cases. This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2).
...
Fixes PR9693.
llvm-svn: 137292
2011-08-11 01:48:05 +00:00
94ba2cba6e
ARM tests for LDRSHT assembly parsing and encoding.
...
llvm-svn: 137274
2011-08-10 23:18:30 +00:00
a6ab52bf9f
ARM tests for LDRSH assembly parsing and encoding.
...
llvm-svn: 137272
2011-08-10 23:12:25 +00:00
2953404723
ARM tests for LDRSBT assembly parsing and encoding.
...
llvm-svn: 137271
2011-08-10 23:08:56 +00:00
c11bbf3bda
ARM tests for LDRSB assembly parsing and encoding.
...
llvm-svn: 137270
2011-08-10 23:06:44 +00:00
35cdf36c32
Add FIXME.
...
llvm-svn: 137265
2011-08-10 22:56:43 +00:00
5e0c9711f2
ARM tests for LDRHT assembly parsing and encoding.
...
llvm-svn: 137263
2011-08-10 22:55:38 +00:00
504769fc2f
test/CodeGen/X86/opt-shuff-tstore.ll: Add explicit -mtriple=x86_64-linux.
...
llvm-svn: 137262
2011-08-10 22:52:48 +00:00
7cd4253cc3
ARM tests for LDRH(register) assembly parsing and encoding.
...
llvm-svn: 137261
2011-08-10 22:45:42 +00:00
cd4dd255c0
ARM LDRH(immediate) assembly parsing and encoding support.
...
llvm-svn: 137260
2011-08-10 22:42:16 +00:00
ae1b002fa3
Add FIXME
...
llvm-svn: 137258
2011-08-10 22:20:38 +00:00
1d9d5e93d1
ARM LDRD(register) assembly parsing and encoding.
...
Add support for literal encoding of #-0 along the way.
llvm-svn: 137254
2011-08-10 21:56:18 +00:00
37a62058fe
While extending definition range of a debug variable, consult lexical scopes also. There is no point extending debug variable out side its lexical block. This provides 6x compile time speedup in some cases.
...
llvm-svn: 137250
2011-08-10 21:25:34 +00:00
5b96b80644
ARM LDRD(immediate) assembly parsing and encoding support.
...
llvm-svn: 137244
2011-08-10 20:29:19 +00:00
d2b071f562
Fix the test. Add cpu target.
...
llvm-svn: 137241
2011-08-10 19:49:19 +00:00
410a11fe82
When performing a truncating store, it is sometimes possible to rearrange the
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data in-register prior to saving to memory. When we reorder the data in memory
we prevent the need to save multiple scalars to memory, making a single regular
store.
llvm-svn: 137238
2011-08-10 19:30:14 +00:00
c86a5bd219
Add initial support for decoding NEON instructions in Thumb2 mode.
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llvm-svn: 137236
2011-08-10 19:01:10 +00:00
3ff111c12d
The following X86 pattern is incorrect:
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def : Pat<(X86Movss VR128:$src1,
(bc_v4i32 (v2i64 (load addr:$src2)))),
(MOVLPSrm VR128:$src1, addr:$src2)>;
This matches a MOVSS dag with a MOVLPS instruction. However, MOVSS will replace only the low 32 bits of the register, while the MOVLPS instruction will replace the low 64 bits. A testcase is added and illustrates the bug and also modified the one that was already present. Patch by Tanya Lattner.
llvm-svn: 137227
2011-08-10 17:45:17 +00:00
36a3abc671
Add support for the R and Q constraints.
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llvm-svn: 137217
2011-08-10 16:26:42 +00:00
4d0040baf8
Invoke SimplifyIndVar when we partially unroll a loop. Fixes PR10534.
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llvm-svn: 137203
2011-08-10 04:29:49 +00:00
278ffd7d8e
Fix a bug in vpermilps mask checking. Fix PR10560
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llvm-svn: 137194
2011-08-10 01:54:17 +00:00
c6bd551db0
Remove the build_unwind function from the OCaml bindings.
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llvm-svn: 137193
2011-08-10 01:10:17 +00:00
b72bbe2a92
Fix the LoopUnroller to handle nontrivial loops and partial unrolling.
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These are not individual bug fixes. I had to rewrite a good chunk of
the unroller to make it sane. I think it was getting lucky on trivial
completely unrolled loops with no early exits. I included some fairly
simple unit tests for partial unrolling. I didn't do much stress
testing, so it may not be perfect, but should be usable now.
llvm-svn: 137190
2011-08-10 00:28:10 +00:00
8059f0cf8d
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
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llvm-svn: 137189
2011-08-10 00:03:03 +00:00
92b942b1b5
Tighten operand checking of register-shifted-register operands.
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llvm-svn: 137180
2011-08-09 23:33:27 +00:00
72323966c8
Add 256-bit support for v8i32, v4i64 and v4f64 ISD::SELECT. Fix PR10556
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llvm-svn: 137179
2011-08-09 23:27:13 +00:00
e008931bf6
Tighten operand checking on memory barrier instructions.
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llvm-svn: 137176
2011-08-09 23:25:42 +00:00
3d2e0e9db6
Tighten operand checking on CPS instructions.
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llvm-svn: 137172
2011-08-09 23:05:39 +00:00
042619f97d
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
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llvm-svn: 137168
2011-08-09 22:48:45 +00:00
fc481959d2
Add v16i16 and v32i8 store patterns
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llvm-svn: 137166
2011-08-09 22:39:53 +00:00
6963062a99
Use fp unpack instructions to unpack int types. Until we have AVX2, this
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is the best we can do for these patterns. This fix PR10554.
llvm-svn: 137161
2011-08-09 22:18:37 +00:00
4ef2426b87
Fix a couple ridiculous copy-paste errors. rdar://9914773 .
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llvm-svn: 137160
2011-08-09 22:17:39 +00:00
406dc1755f
ARM Disassembler: sign extend branch immediates.
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Not sure about BLXi, but this is what the old disassembler did.
llvm-svn: 137156
2011-08-09 22:02:50 +00:00
7a2401dbf0
Tighten Thumb1 branch predicate decoding.
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llvm-svn: 137146
2011-08-09 21:07:45 +00:00
e0152a73c2
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
llvm-svn: 137144
2011-08-09 20:55:18 +00:00
d7f41b7f66
Revert r137134. It breaks some code as Eli pointed out.
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llvm-svn: 137135
2011-08-09 18:56:35 +00:00
84ec8f65d1
Print out the variable declaration only if it is a declaration. Otherwise, a
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'static' variable will be emitted twice.
PR10081
llvm-svn: 137134
2011-08-09 18:31:50 +00:00
53910d6aae
Inflate register classes after coalescing.
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Coalescing can remove copy-like instructions with sub-register operands
that constrained the register class. Examples are:
x86: GR32_ABCD:sub_8bit_hi -> GR32
arm: DPR_VFP2:ssub0 -> DPR
Recompute the register class of any virtual registers that are used by
less instructions after coalescing.
This affects code generation for the Cortex-A8 where we use NEON
instructions for f32 operations, c.f. fp_convert.ll:
vadd.f32 d16, d1, d0
vcvt.s32.f32 d0, d16
The register allocator is now free to use d16 for the temporary, and
that comes first in the allocation order because it doesn't interfere
with any s-registers.
llvm-svn: 137133
2011-08-09 18:19:41 +00:00
bed48dc8ff
Reapply a more appropriate solution than in r137114. AVX supports
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v4f64 = sitofp v4i32. This fix PR10559.
Also add support for v4i32 = fptosi v4f64.
llvm-svn: 137128
2011-08-09 17:39:13 +00:00
24dd1d4a27
Revert r137114
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llvm-svn: 137127
2011-08-09 17:39:01 +00:00
db05c2b963
PTX: Add initial support for device function calls
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- Calls are supported on SM 2.0+ for function with no return values
llvm-svn: 137125
2011-08-09 17:36:31 +00:00
ad3453cf2d
Handle sitofp between v4f64 <- v4i32. Fix PR10559
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llvm-svn: 137114
2011-08-09 05:48:01 +00:00
1155b1eafa
Add support for avx vector fextend
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llvm-svn: 137105
2011-08-09 03:04:29 +00:00
337a7fdb13
Rename and tidy up tests
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llvm-svn: 137103
2011-08-09 03:04:23 +00:00
2fc107365b
Add two patterns to match special vmovss and vmovsd cases. Also fix
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the patterns already there to be more strict regarding the predicate.
This fixes PR10558
llvm-svn: 137100
2011-08-09 01:43:09 +00:00
af6a85484c
Make LowerVSETCC aware of AVX types and add patterns to match them.
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llvm-svn: 137090
2011-08-09 00:46:57 +00:00
b24a1d29cb
Tidy up these testcases to look more like real code does.
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llvm-svn: 137085
2011-08-09 00:33:11 +00:00
cab35c0836
ARM parsing and encoding for LDRBT instruction.
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Fix the instruction representation to correctly only allow post-indexed form.
Add tests.
llvm-svn: 137074
2011-08-08 23:28:47 +00:00
5838c0c47e
ARM parsing and encoding for LDRB instruction.
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llvm-svn: 137071
2011-08-08 22:37:06 +00:00
f6dbc3a57c
Add FIXME.
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llvm-svn: 137070
2011-08-08 22:11:33 +00:00
c96953c12a
Add support for several vector shifts operations while in AVX mode. Fix PR10581
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llvm-svn: 137067
2011-08-08 21:31:08 +00:00
a27da98921
Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611.
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llvm-svn: 137061
2011-08-08 19:49:37 +00:00
4f0ace5674
Don't clobber pending ST regs when FP regs are killed.
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X86FloatingPoint keeps track of pending ST registers for an upcoming
inline asm instruction with fixed stack register constraints. It does
this by remembering which FP register holds the value that should appear
at a fixed stack position for the inline asm.
When that FP register is killed before the inline asm, make sure to
duplicate it to a scratch register, so the ST register still has a live
FP reference.
This could happen when the same FP register was copied to two ST
registers, or when a spill instruction is inserted between the ST copy
and the inline asm.
This fixes PR10602.
llvm-svn: 137050
2011-08-08 17:15:43 +00:00
6d45a01b67
Made SCEV's UDiv expressions more canonical. When dividing a
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recurrence, the initial values low bits can sometimes be ignored.
To take advantage of this, added FoldIVUser to IndVarSimplify to fold
an IV operand into a udiv/lshr if the operator doesn't affect the
result.
-indvars -disable-iv-rewrite now transforms
i = phi i4
i1 = i0 + 1
idx = i1 >> (2 or more)
i4 = i + 4
into
i = phi i4
idx = i0 >> ...
i4 = i + 4
llvm-svn: 137013
2011-08-06 07:00:37 +00:00
3d0b3a3a50
ARM load instruction shifted register index operands.
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Parsing and encoding for shifted index operands for load instructions.
llvm-svn: 136986
2011-08-05 22:03:36 +00:00
c320c85261
ARM indexed load assembly parsing and encoding.
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More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.
llvm-svn: 136982
2011-08-05 21:28:30 +00:00
0f2dd284e9
Add ARM LDR parsing tests.
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llvm-svn: 136977
2011-08-05 20:33:39 +00:00
c0174048a4
We need to map DebugLoc. It leads to Fuction * (through subprogram entry node) which should be appropriately mapped.
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llvm-svn: 136910
2011-08-04 20:02:18 +00:00
6ddbb2e277
Linke NamedMDNodes after linking global values as comment suggests.
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llvm-svn: 136909
2011-08-04 19:44:28 +00:00
77dde89b90
Fix the bitwidth of the remaining fields.
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llvm-svn: 136884
2011-08-04 17:00:11 +00:00
9bc32a96be
print st_shndx with the correct number of bits.
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llvm-svn: 136880
2011-08-04 15:50:13 +00:00
9528995e3f
print st_other with the correct number of bits.
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llvm-svn: 136877
2011-08-04 15:38:19 +00:00
96df560ce1
print st_type with the correct number of bits.
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llvm-svn: 136875
2011-08-04 15:24:00 +00:00
79ef75dc49
Print st_bind with the correct number of bits.
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llvm-svn: 136874
2011-08-04 15:10:35 +00:00
1848231ad1
Print r_sym with the correct number of bits.
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llvm-svn: 136873
2011-08-04 14:48:27 +00:00
260af5cef6
Print r_type with the correct number of bits.
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llvm-svn: 136872
2011-08-04 14:39:30 +00:00
1b282e7e49
Another counter goes decimal.
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llvm-svn: 136871
2011-08-04 14:27:46 +00:00
65c559c5fb
Change anther counter to decimal.
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llvm-svn: 136870
2011-08-04 14:01:03 +00:00
cad9e7f094
Don't print a counter in hex.
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llvm-svn: 136869
2011-08-04 13:39:15 +00:00
69c67d3b18
Print all the bits in the addend.
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llvm-svn: 136867
2011-08-04 13:00:24 +00:00
e4df09f7ba
Fix http://llvm.org/bugs/show_bug.cgi?id=10568
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Move the reloc size assert into AsmBackend - where it is more apropos.
llvm-svn: 136855
2011-08-04 00:38:45 +00:00
e234f6ae0c
Only access both operands of an INSERT_SUBVECTOR if it is an INSERT_SUBVECTOR.
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Fixes PR10527.
llvm-svn: 136853
2011-08-04 00:32:58 +00:00
d359571120
ARM refactoring assembly parsing of memory address operands.
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Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
llvm-svn: 136845
2011-08-03 23:50:40 +00:00
3c7e9ee480
Remove underscore that's breaking linux buildbots.
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llvm-svn: 136833
2011-08-03 23:13:01 +00:00
15e5b742ad
Use MachineBranchProbabilityInfo in If-Conversion instead of its own heuristics.
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llvm-svn: 136826
2011-08-03 22:34:43 +00:00
2d3138c112
Remove the LowerSetJmp pass. It wasn't used effectively by any of the targets.
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This is some of my original LLVM code. *wipes tear*
llvm-svn: 136821
2011-08-03 22:18:20 +00:00
bf69d03382
SCEV: Use AssertingVH to catch dangling BasicBlock* when passes forget
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to notify SCEV of a change. Add forgetLoop in a couple of those places.
llvm-svn: 136797
2011-08-03 18:32:11 +00:00
da618420ee
Handle IMPLICIT_DEF instructions in X86FloatingPoint.
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This fixes PR10575.
llvm-svn: 136787
2011-08-03 16:33:19 +00:00
5b82a0ac0c
fix PR10286, a problem with the .ll printer handling block addresses that are out-of-scope.
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llvm-svn: 136768
2011-08-03 06:15:41 +00:00
dc9cbaaf23
Use byte offset, instead of element number, to access merged global.
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llvm-svn: 136759
2011-08-03 01:25:46 +00:00
50f4966ceb
Fix logical error when detecting lifetime intrinsics.
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Don't replace a gep/bitcast with 'undef' because that will form a "free(undef)"
which in turn means "unreachable". What we wanted was a no-op. Instead, analyze
the whole tree and look for all the instructions we need to delete first, then
delete them second, not relying on the use_list to stay consistent.
llvm-svn: 136752
2011-08-03 00:43:35 +00:00
e8ae02dfb9
Teach InstCombine that lifetime intrincs aren't a real user on the result of a
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malloc call.
llvm-svn: 136732
2011-08-02 22:08:01 +00:00
99890a225f
Lifetime intrinsics on undef are dead.
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llvm-svn: 136722
2011-08-02 21:19:27 +00:00
c48e10cd54
Assume .cfi_startproc is the first thing in a function. If the function is
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externally visable, create a local symbol to use in the CFE. If not, use the
function label itself.
Fixes PR10420.
llvm-svn: 136716
2011-08-02 20:24:22 +00:00
5ada908140
Make this kind of lowering to be supported by 256-bit instructions:
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shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
To:
shuffle (vload ptr)), undef, <1, 1, 1, 1>
Fix PR10494
llvm-svn: 136691
2011-08-02 16:06:18 +00:00
c4189ff0fc
Remove empty test.
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llvm-svn: 136675
2011-08-02 02:47:45 +00:00
bddf40e082
Revert r136503 and r136480 in an effort to fix non-determinism in the llvm-gcc buildbots on i386. Devang is looking into the root cause.
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llvm-svn: 136674
2011-08-02 02:23:42 +00:00
a8e3673816
Add v4f64 -> v2f32 fp_round support. Also add a testcase to exercise
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the legalizer. This commit together with the two previous ones fixes
PR10495.
llvm-svn: 136654
2011-08-01 21:54:09 +00:00
7513939ddd
Since vectors with all ones can't be created with a 256-bit instruction,
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avoid returning early for v8i32 types, which would only be valid for
vector with all zeros. Also split the handling of zeros and ones into separate
checking logic since they are handled differently. This fixes PR10547
llvm-svn: 136642
2011-08-01 19:51:53 +00:00
0cc000ef29
Fix crash with varargs function with no named parameters.
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llvm-svn: 136623
2011-08-01 16:45:59 +00:00
a3a44f3fc3
Add a small gep optimization I noticed was missing while reading some IL.
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llvm-svn: 136585
2011-07-31 04:43:41 +00:00
99d53ff456
Remove InvalidateStructLayoutInfo from the ocaml bindings.
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llvm-svn: 136582
2011-07-31 01:12:39 +00:00
ad088e6724
Revert r136253, r136263, r136269, r136313, r136325, r136326, r136329, r136338,
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r136339, r136341, r136369, r136387, r136392, r136396, r136429, r136430, r136444,
r136445, r136446, r136253 pending review.
llvm-svn: 136556
2011-07-30 05:42:50 +00:00
5670f850c6
Revert "Don't check liveness of unallocatable registers."
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The ARM target depends on CPSR liveness being tracked after register
allocation.
llvm-svn: 136548
2011-07-30 00:57:25 +00:00
95cc5440e9
Don't check liveness of unallocatable registers.
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This includes registers like EFLAGS and ST0-ST7. We don't check for
liveness issues in the verifier and scavenger because registers will
never be allocated from these classes.
While in SSA form, we do care about the liveness of unallocatable
unreserved registers. Liveness of EFLAGS and ST0 neds to be correct for
MachineDCE and MachineSinking.
llvm-svn: 136541
2011-07-29 23:36:21 +00:00
Bruno Cardoso Lopes