Commit Graph

228538 Commits

Author SHA1 Message Date
Sagar Thakur b1c51f6a94 [ASAN] Use struct instead of array in sancov.py
Summary: When using 32-bit python with 64-bit asan the pc array in sancov.py cannot fit in 64-bit pc's because the type-code 'L' for
arrays in python corresponds to the C type long which is only of 4 bytes. Because of this some of the coverage tool tests fail on
mips. To fix these test possible solutions are to use 64-bit python or use struct.unpack with the 'Q' type-code. We have used
struct.unpack with 'Q' type code since it is not appropriate to have a 64-bit python on all hosts.

Reviewed by kcc, aizatsky

Differential: http://reviews.llvm.org/D18817
llvm-svn: 267126
2016-04-22 09:20:22 +00:00
Alexey Bataev feddd64bff [OPENMP] Fix for PR27463: Privatizing struct fields with array type
causes code generation failure.

The codegen part of firstprivate clause for member decls used type of
original variable without skipping reference type from
OMPCapturedExprDecl. Patch fixes this problem.

llvm-svn: 267125
2016-04-22 09:05:03 +00:00
Pavel Labath 69ef42cc42 Update comment in lldb-enumerations.h
llvm-svn: 267124
2016-04-22 08:41:07 +00:00
Ashutosh Nema 468558a061 [X86]: Changing cost for “TRUNCATE v16i32 to v16i8” in SSE4.1 mode.
Summary:
rL256194 transforms truncations between vectors of integers into PACKUS/PACKSS
operations during DAG combine. This generates better code for truncate, so cost
of truncate needs to be changed but looks like it got changed only in SSE2 table
Whereas this change is also applicable for SSE4.1, so the cost of truncate needs
to be changed for that as well. Cost of “TRUNCATE v16i32 to v16i8” & “TRUNCATE 
v16i16 to v16i8” should be same in SSE4.1 & SSE2 table. Removing their cost from
SSE4.1, so it will fall back to SSE2.

Reviewers: Simon Pilgrim
llvm-svn: 267123
2016-04-22 08:34:05 +00:00
Chris Dewhurst 6019702960 [Sparc] This provides support for itineraries on Sparc.
Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future.

The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this.

As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary.

Phabricator Review: http://reviews.llvm.org/D19359

llvm-svn: 267121
2016-04-22 08:17:17 +00:00
Chris Dewhurst 431fc8af7b The following code would not work before this patch, due to the inability to take the address of a global object:
void func1() {

...
}

int main(int argc, char** argv) {

void (*pFunc)();
pFunc = &func1
pFunc();
...
}

Phabricator review: http://reviews.llvm.org/D19368

llvm-svn: 267120
2016-04-22 08:13:47 +00:00
Marshall Clow f8997cf5ae Add missing include of <algorithm>
llvm-svn: 267119
2016-04-22 07:39:05 +00:00
Argyrios Kyrtzidis 0642a21f1d [index] Add SymbolSubKinds for ObjC IB annotations.
llvm-svn: 267118
2016-04-22 07:21:16 +00:00
Argyrios Kyrtzidis f30c8c621f [index] Add a SymbolSubKind for an ObjC unit test.
llvm-svn: 267117
2016-04-22 07:21:10 +00:00
Argyrios Kyrtzidis f2142cbca8 [index] Change SymbolCXXTemplateKind to a 'SymbolSubKinds' bitset.
This provides a more general and flexible way to annotate special symbols.

llvm-svn: 267116
2016-04-22 07:21:04 +00:00
Vedant Kumar 6013f45f92 Revert "Initial implementation of optimization bisect support."
This reverts commit r267022, due to an ASan failure:

  http://lab.llvm.org:8080/green/job/clang-stage2-cmake-RgSan_check/1549

llvm-svn: 267115
2016-04-22 06:51:37 +00:00
Zlatko Buljan ae720dbbb6 [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructions
Differential Revision: http://reviews.llvm.org/D18687

llvm-svn: 267114
2016-04-22 06:44:34 +00:00
David Majnemer d0ce8f1485 [GVN] Respect fast-math-flags on fcmps
We assumed that flags were only present on binary operators.  This is
not true, they may also be present on calls and fcmps.

llvm-svn: 267113
2016-04-22 06:37:51 +00:00
David Majnemer 68318e0414 Fix some spelling mistakes
llvm-svn: 267112
2016-04-22 06:37:48 +00:00
David Majnemer 9554c1339c [EarlyCSE] Take the intersection of flags on instructions
EarlyCSE had inconsistent behavior with regards to flag'd instructions:
- In some cases, it would pessimize if the available instruction had
  different flags by not performing CSE.
- In other cases, it would miscompile if it replaced an instruction
  which had no flags with an instruction which has flags.

Fix this by being more consistent with our flag handling by utilizing
andIRFlags.

llvm-svn: 267111
2016-04-22 06:37:45 +00:00
Sanjoy Das efdeb45ffd [SCEV] Extract out a `isSCEVExprNeverPoison` helper; NFCI
Summary:
Also adds a small comment blurb on control flow + no-wrap flags, since
that question came up a few days back on llvm-dev.

Reviewers: bjarke.roune, broune

Subscribers: sanjoy, mcrosier, llvm-commits, mzolotukhin

Differential Revision: http://reviews.llvm.org/D19209

llvm-svn: 267110
2016-04-22 05:38:54 +00:00
Craig Topper 591fc065c8 [SystemZ] Mark CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF as Expand instead of Custom since the custom logic just did what Expand does when CTTZ/CTLZ are Legal. NFC
llvm-svn: 267109
2016-04-22 05:29:58 +00:00
Craig Topper 444317bb33 [Lanai] Set CTLZ_ZERO_UNDEF/CTTZ_ZERO_UNDEF to Expand instead of Legal so they will be converted to CTLZ/CTTZ by LegalizeDAG. Remove extra instructions that only existed to to contain patterns that match the zero_undef operations. NFC
llvm-svn: 267108
2016-04-22 05:13:01 +00:00
Craig Topper 47d0409668 [Lanai] Remove unused methods declarations. NFC
llvm-svn: 267107
2016-04-22 05:12:57 +00:00
Mehdi Amini a0cb890fb6 Clean the API for CollectAsmUndefinedRefs, taking a Triple and a String InlineAsm instead of a Module (NFC)
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 267106
2016-04-22 04:58:12 +00:00
Mehdi Amini 9ff43e40fa IRObjectFile, clang-format fixup for r267104
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 267105
2016-04-22 04:49:46 +00:00
Mehdi Amini 9a1724bf3d Use std::move on the enum to insert it into the pair to please MSVC
(I have no idea why is it needed)
Fixup for r267103

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 267104
2016-04-22 04:45:57 +00:00
Mehdi Amini e9cffafdf7 Refactor IRObjectFile, extract a static CollectAsmUndefinedRefs() method to parse inline assembly (NFC)
I plan to call this from ThinLTOCodeGenerator.

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 267103
2016-04-22 04:28:05 +00:00
Nicolai Haehnle b0c9748709 AMDGPU/SI: add llvm.amdgcn.ps.live intrinsic
Summary:
This intrinsic returns true if the current thread belongs to a live pixel
and false if it belongs to a pixel that we are executing only for derivative
computation. It will be used by Mesa to implement gl_HelperInvocation.

Note that for pixels that are killed during the shader, this implementation
also returns true, but it doesn't matter because those pixels are always
disabled in the EXEC mask.

This unearthed a corner case in the instruction verifier, which complained
about a v_cndmask 0, 1, exec, exec<imp-use> instruction. That's stupid but
correct code, so make the verifier accept it as such.

Reviewers: arsenm, tstellarAMD

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D19191

llvm-svn: 267102
2016-04-22 04:04:08 +00:00
Alexey Bataev 5dff95c04d [OPENMP] Fix for LCV in simd directives in explicit clauses.
If loop control variable for simd-based directives is explicitly marked
as linear/lastprivate in clauses, codegen for such construct would
crash. Patch fixes this problem.

llvm-svn: 267101
2016-04-22 03:56:56 +00:00
Craig Topper 59479e7208 [AVX512] Teach lowering to use vplzcntd/q to implement 128/256-bit CTTZ_ZERO_UNDEF even without VLX support. We can just extend to 512-bits and extract like we do for CTLZ.
llvm-svn: 267100
2016-04-22 03:22:38 +00:00
Duncan P. N. Exon Smith 71480bd0c7 ValueMapper/Enumerator: Clean up code in post-order traversals, NFC
Re-layer the functions in the new (i.e., newly correct) post-order
traversals in ValueEnumerator (r266947) and ValueMapper (r266949).
Instead of adding a node to the worklist in a helper function and
returning a flag to say what happened, return the node itself.  This
makes the code way cleaner: the worklist is local to the main function,
there is no flag for an early loop exit (since we can cleanly bury the
loop), and it's perfectly clear when pointers into the worklist might be
invalidated.

I'm fixing both algorithms in the same commit to avoid repeating the
commit message; if you take the time to understand one the other should
be easy.  The diff itself isn't entirely obvious since the traversals
have some noise (i.e., things to do), but here's the high-level change:

    auto helper = [&WL](T *Op) {     auto helper = [](T **&I, T **E) {
                                 =>    while (I != E) {
      if (shouldVisit(Op)) {             T *Op = *I++;
        WL.push(Op, Op->begin());        if (shouldVisit(Op)) {
        return true;                       return Op;
      }                                }
      return false;                    return nullptr;
    };                               };
                                 =>
    WL.push(S, S->begin());          WL.push(S, S->begin());
    while (!empty()) {               while (!empty()) {
      auto *N = WL.top().N;            auto *N = WL.top().N;
      auto *&I = WL.top().I;           auto *&I = WL.top().I;
      bool DidChange = false;
      while (I != N->end())
        if (helper(*I++)) {      =>    if (T *Op = helper(I, N->end()) {
          DidChange = true;              WL.push(Op, Op->begin());
          break;                         continue;
        }                              }
      if (DidChange)
        continue;

      POT.push(WL.pop());        =>    POT.push(WL.pop());
    }                                }

Thanks to Mehdi for helping me find a better way to layer this.

llvm-svn: 267099
2016-04-22 02:33:06 +00:00
Gerolf Hoflehner b32f11fc62 [MachineCombiner] Support for floating-point FMA on ARM64
Evaluates fmul+fadd -> fmadd combines and similar code sequences in the
machine combiner. It adds support for float and double similar to the existing
integer implementation. The key features are:

- DAGCombiner checks whether it should combine greedily or let the machine
combiner do the evaluation. This is only supported on ARM64.
- It gives preference to throughput over latency: the heuristic used is
to combine always in loops. The targets decides whether the machine
combiner should optimize for throughput or latency.
- Supports for fmadd, f(n)msub, fmla, fmls patterns
- On by default at O3 ffast-math

llvm-svn: 267098
2016-04-22 02:15:19 +00:00
Teresa Johnson 6fb3f19959 [ThinLTO] Remove unused/incomplete lazy summary reading support (NFC)
This removes the interfaces added (and not yet complete) to support
lazy reading of summaries. This support is not expected to be needed
since we are moving to a model where the full index is only being
traversed in the thin link step, instead of the back ends.

(The second part of this that I plan to do next is remove the
GlobalValueInfo from the ModuleSummaryIndex - it was mostly needed to
support lazy parsing of summaries. The index can instead reference the
summary structures directly.)

llvm-svn: 267097
2016-04-22 01:52:00 +00:00
NAKAMURA Takumi adbab8638c Untabify.
llvm-svn: 267096
2016-04-22 01:33:50 +00:00
Nico Weber f3fc748308 Try to fix UNRESOLVED: LLVM :: CodeGen/AArch64/arm64-regress-opt-cmp.s on bots.
This test used to write a .s file until r266971 fixed that.  But on most bots,
the .s file still exists.  Add an rm statement to clean up the bots.  In a few
days, this statement can go away again.

llvm-svn: 267095
2016-04-22 01:08:56 +00:00
Kostya Serebryany d55d0875d2 [sanitizer] Allow the sanitizer allocator to use a non-fixed address range. An allocator with a non-fixed address range will be attack-resistan. NFC for the sanitizers at this point.
llvm-svn: 267094
2016-04-22 01:08:54 +00:00
Evgeniy Stepanov cd31b4348a Cleanup: move visibility/linkage attributes to the first declaration.
http://reviews.llvm.org/D15404

llvm-svn: 267093
2016-04-22 01:04:55 +00:00
Saleem Abdulrasool 12b87facf4 ARM: fix test for Windows division
This was meant to be part of SVN r267080.  cbz cannot use a high register, which
would be silently truncated.  This has now been fixed.

llvm-svn: 267092
2016-04-22 01:03:38 +00:00
Eric Fiselier 906c50859b Fix LWG issue #2106: move_iterators returning prvalues
llvm-svn: 267091
2016-04-22 00:49:12 +00:00
Eric Fiselier b7f045fc7d Fix C++03 build breakage
llvm-svn: 267090
2016-04-22 00:47:15 +00:00
Nico Weber 379609329d Try to get test passing on OS X (see comment at top of file).
llvm-svn: 267089
2016-04-22 00:38:09 +00:00
Evgeniy Stepanov 988ebe9f34 [asan] Disable one test on windows.
Patch by Vitaly Buka.

llvm-svn: 267088
2016-04-22 00:34:10 +00:00
NAKAMURA Takumi 70191d628f clangTidyReadabilityModule: Add clangTidyUtils in libdeps, corresponding to r267003.
llvm-svn: 267087
2016-04-22 00:33:39 +00:00
Rui Ueyama c9f402eadc Inline SectionRule::match.
This short function was used only once and didn't provide much value.

llvm-svn: 267086
2016-04-22 00:23:52 +00:00
Eric Fiselier d513ad88d5 Complete LWG issue #2016. Allocators must be nothrow swappable
llvm-svn: 267085
2016-04-22 00:15:18 +00:00
Evgeniy Stepanov 4c0f6afbab Enable stack-use-after-scope tests.
Fix and enable working stack-use-after-scope tests.
Add more failing tests for the feature, for fix later.

PR27453.

Patch by Vitaly Buka.

llvm-svn: 267084
2016-04-22 00:10:23 +00:00
Rui Ueyama c998a8c044 ELF: Make the special variable "." as a LinkerScript class member.
I will eventually make `evaluate` function a usual parse function
rather than a function that works on a separate token list.
This is the first step toward that.

llvm-svn: 267083
2016-04-22 00:03:13 +00:00
Dan Gohman 04e7fb778d [WebAssembly] Limit alignment hints to natural alignment.
This follows the current binary format rules.

llvm-svn: 267082
2016-04-21 23:59:48 +00:00
Rafael Espindola 5be6064974 Don't gc protected symbols.
llvm-svn: 267081
2016-04-21 23:59:19 +00:00
Saleem Abdulrasool a028853540 ARM: restrict register class for WIN__DBZCHK
WIN__DBZCHK will insert a CBZ instruction into the stream.  This instruction
reserves 3 bits for the condition register (rn).  As such, we must ensure that
we restrict the register to a low register.  Use the tGPR class instead of GPR
to ensure that this is properly constrained.  In debug builds, we would attempt
to use lr as a condition register which would silently get truncated with no
hint that the register selection was incorrect.

llvm-svn: 267080
2016-04-21 23:53:19 +00:00
Eric Fiselier f07dd8d0a9 Add is_swappable/is_nothrow_swappable traits
llvm-svn: 267079
2016-04-21 23:38:59 +00:00
Mike Aizatsky c89755e4cb [sancov] using normalized filenames for blacklist checks.
Differential Revision: http://reviews.llvm.org/D19395

llvm-svn: 267078
2016-04-21 23:38:45 +00:00
David Blaikie f0f6c29cec Fix more -Wunused-variable in non-asserts build.
llvm-svn: 267077
2016-04-21 23:24:09 +00:00
Eric Fiselier 62b98b6cce Make ios_base::failure visibility specified consistent
llvm-svn: 267076
2016-04-21 23:00:33 +00:00