f6ac018926
Fix typos in (generated) comments.
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llvm-svn: 55916
2008-09-08 16:29:36 +00:00
ca14c07175
Correctly handle physical register inputs. They are not explicit input operands in the resulting machine instrs.
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llvm-svn: 55893
2008-09-08 08:39:33 +00:00
105c581135
Eliminate a compile time warning.
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llvm-svn: 55878
2008-09-07 09:00:57 +00:00
09638d34a5
Fix indentation of generated code.
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llvm-svn: 55876
2008-09-07 08:23:06 +00:00
7cab17af29
Ignore multi-instruction patterns. e.g.
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def : Pat<(i8 (trunc GR32:$src)),
(i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>
llvm-svn: 55875
2008-09-07 08:19:51 +00:00
24422d4928
Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class.
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llvm-svn: 55679
2008-09-03 00:03:49 +00:00
34f3a962b0
Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes.
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llvm-svn: 55623
2008-09-02 06:51:36 +00:00
0673a8af14
Add initial support for fast isel of instructions that have inputs pinned to physical registers.
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llvm-svn: 55545
2008-08-29 17:45:56 +00:00
d58f3e36d0
Add a target callback for FastISel.
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llvm-svn: 55512
2008-08-28 23:21:34 +00:00
f304a7aa4d
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
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llvm-svn: 55504
2008-08-28 21:40:38 +00:00
787f100462
Add support for fast-isel of opcodes that require use of extract_subreg. Because of how extract_subreg is treated, it requires special case handling.
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llvm-svn: 55480
2008-08-28 18:06:12 +00:00
6d153b02c9
Update a comment to reflect recent changes.
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llvm-svn: 55418
2008-08-27 16:18:22 +00:00
5ca269e684
Basic FastISel support for floating-point constants.
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llvm-svn: 55401
2008-08-27 01:09:54 +00:00
abfdf928d8
disallow direct access to SDValue::ResNo, provide a getter instead
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llvm-svn: 55394
2008-08-26 22:36:50 +00:00
44003cc354
Refactor a bunch of FastISelEmitter code into a helper class, and
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put each major step in a separate function. This makes the high
level sequence of events easier to follow.
llvm-svn: 55385
2008-08-26 21:21:20 +00:00
cf7154b2d6
- small bug corrected: incorrect iterator type.
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- fix to please VS: add a return after an assert.
llvm-svn: 55380
2008-08-26 19:49:04 +00:00
3ea3efec44
We need to check that the return type is correct, even in cases where we don't
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have a return type that differs from the operand types.
llvm-svn: 55376
2008-08-26 18:50:00 +00:00
491a930ea3
code simplification, no functionality change.
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llvm-svn: 55363
2008-08-26 07:01:28 +00:00
345dcce5a6
stabilize more printing, this doesn't cause a problem
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in the example attached to PR2590, but is a problem in general.
llvm-svn: 55361
2008-08-26 06:50:46 +00:00
ef820d2ef9
stablize SubRegsSet printing, part of PR2590
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llvm-svn: 55360
2008-08-26 06:49:06 +00:00
bd7ccd0162
Stabilize 'getDwarfRegNumFull' output to not depend on random memory
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orders, part of PR2590
llvm-svn: 55359
2008-08-26 06:43:25 +00:00
6f2db7238b
Throw the switch to allow FastISel to emit instructions whose return types different from their inputs. Next step: adding lowering pattens in FastISel that actually use these newly available opcodes.
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llvm-svn: 55349
2008-08-26 01:22:59 +00:00
5f334d8215
Enhance TableGen to emit code for FastISel of opcodes with variadic return types without slowing down opcodes that are not variadic. No such opcodes are currently generated, but in theory it should be a matter of just hitting the switch.
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llvm-svn: 55347
2008-08-26 00:42:26 +00:00
8dd01ccdd8
Add a RetVT parameter to emitted FastISel methods, so that we will be able to pass the desired return
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type down. This is not currently used.
llvm-svn: 55345
2008-08-25 23:58:18 +00:00
5952cca7d1
Deepen the map structure tablegen uses to compute FastISel patterns, in preparation for having patterns
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with return types that differ from their input types. This is not yet used.
llvm-svn: 55344
2008-08-25 23:43:09 +00:00
32635dbfb2
Add support for fast isel of (integer) immediate materialization pattens, and use them to support
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bitcast of constants in fast isel.
llvm-svn: 55325
2008-08-25 20:20:32 +00:00
eb0cee91f6
Move the point at which FastISel taps into the SelectionDAGISel
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process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.
Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.
To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.
llvm-svn: 55219
2008-08-23 02:25:05 +00:00
9b29ec7ba9
Add a few comments.
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llvm-svn: 55157
2008-08-22 00:28:15 +00:00
49e19e906f
Factor out the predicate check code from DAGISelEmitter.cpp
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and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.
llvm-svn: 55156
2008-08-22 00:20:26 +00:00
fe9056584b
Basic fast-isel support for instructions with constant int operands.
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llvm-svn: 55099
2008-08-21 01:41:07 +00:00
7b3932e5d8
Remove the code that limited FastISel to certain fixed signatures.
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llvm-svn: 55096
2008-08-21 00:35:26 +00:00
7170623b16
Begin making more use of the FastISelEmitter class.
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llvm-svn: 55093
2008-08-21 00:19:05 +00:00
e6724d404b
Remove an obsolete todo comment.
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llvm-svn: 55080
2008-08-20 21:47:28 +00:00
3e2225dfd6
Factor the code for determining the target-specific instruction
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namespace out of the isel emitters and into common code.
llvm-svn: 55079
2008-08-20 21:45:57 +00:00
02c84b8910
Simplify FastISel's constructor argument list, make the FastISel
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class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.
llvm-svn: 55076
2008-08-20 21:05:57 +00:00
b93b489c54
Fix the string for MVT::isVoid.
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llvm-svn: 55034
2008-08-20 01:44:30 +00:00
2dbebd7db5
For now, restrict FastISel to instructions that only involve one
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register class.
llvm-svn: 55008
2008-08-19 20:58:14 +00:00
98e6f1c48a
Factor out the code to scan an instruction's operands into a
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helper function.
llvm-svn: 55007
2008-08-19 20:56:30 +00:00
aa13b6f71b
Add more comments.
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llvm-svn: 55004
2008-08-19 20:36:33 +00:00
49520b99a3
Fix indentation in FastISel tablegen-emitted code.
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llvm-svn: 55003
2008-08-19 20:31:38 +00:00
a6c14d0ddb
Add more checking to filter out more kinds of things that
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FastISel doesn't support yet.
llvm-svn: 55002
2008-08-19 20:30:54 +00:00
6a36fe912c
80 columns.
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llvm-svn: 54998
2008-08-19 18:07:49 +00:00
dbd5328238
Add a few doxygen comments.
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llvm-svn: 54997
2008-08-19 18:06:12 +00:00
522012fc56
Remove an unneeded #include.
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llvm-svn: 54996
2008-08-19 17:53:16 +00:00
fa8b2ea41b
Speed up addRegisterDead by adding more fast checks before performing the expensive
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subregister query, and by increasing the size of the subregister hashtable so
that there are fewer collisions.
llvm-svn: 54781
2008-08-14 18:34:18 +00:00
b2226e21c3
Initial checkin of the new "fast" instruction selection support. See
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the comments in FastISelEmitter.cpp for details on what this is.
This is currently experimental and unusable.
llvm-svn: 54751
2008-08-13 20:19:35 +00:00
e81ac0b66f
Oops, check in these files too, for the FastISel -> Fast rename.
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llvm-svn: 54750
2008-08-13 19:55:00 +00:00
2c839d4b1e
Added support for overloading intrinsics (atomics) based on pointers
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to different address spaces. This alters the naming scheme for those
intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32
llvm-svn: 54195
2008-07-30 04:36:53 +00:00
2ce6f2ad5e
Rename SDOperand to SDValue.
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llvm-svn: 54128
2008-07-27 21:46:04 +00:00
1705968102
Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
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replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.
Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.
This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.
These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.
llvm-svn: 53728
2008-07-17 19:10:17 +00:00
Dan Gohman