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Author SHA1 Message Date
Simi Pallipurath 75c6bfeac9 [ARM]Decoding MSR with unpredictable destination register causes an assert 
This patch handling:

    Enable parsing of raw encodings of system registers .
    Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing.
    Disassemble msr/mrs with unpredictable sysregs as SoftFail.
    Fix regression due to SoftFailing some encodings.

Patch by Chris Ryder

Differential revision:https://reviews.llvm.org/D43374

llvm-svn: 326803
 2018-03-06 15:21:19 +00:00
Mandeep Singh Grang 029a0567fa [LLVM] Remove unwanted --check-prefix=CHECK from unit tests. NFC. 
Summary: Removed unwanted --check-prefix=CHECK from numerous unit tests.

Reviewers: t.p.northover, dblaikie, uweigand, MatzeB, tstellarAMD, mcrosier

Subscribers: mcrosier, dsanders

Differential Revision: http://reviews.llvm.org/D19279

llvm-svn: 266834
 2016-04-19 23:51:52 +00:00
Renato Golin 92c816c68f Thumb2 M-class MSR instruction support changes 
This patch implements a few changes related to the Thumb2 M-class MSR instruction:
 * better handling of unpredictable encodings,
 * recognition of the _g and _nzcvqg variants by the asm parser only if the DSP
   extension is available, preferred output of MSR APSR moves with the _<bits>
   suffix for v7-M.

Patch by Petr Pavlu.

llvm-svn: 216874
 2014-09-01 11:25:07 +00:00
James Molloy 137ce60ecf Allow only disassembling of M-class MSR masks that the assembler knows how to assemble back. 
Note: The current code in DecodeMSRMask() rejects the unpredictable A/R MSR mask '0000' with Fail. The code in the patch follows this style and rejects unpredictable M-class MSR masks also with Fail (instead of SoftFail). If SoftFail is preferred in this case then additional changes to ARMInstPrinter (to print non-symbolic masks) and ARMAsmParser (to parse non-symbolic masks) will be needed.

Patch by Petr Pavlu!

llvm-svn: 214505
 2014-08-01 12:42:11 +00:00