a8821624d4
simplify some code
...
llvm-svn: 25791
2006-01-29 20:01:35 +00:00
1af077c0c7
it is nice not to chop off bits for those blessed with lots of bits
...
llvm-svn: 25766
2006-01-29 05:22:37 +00:00
49f323a90e
make the casts actually cast to the variable type
...
llvm-svn: 25765
2006-01-29 05:17:22 +00:00
c438c51e82
start of the 64bit safety cleanup
...
llvm-svn: 25764
2006-01-29 05:07:04 +00:00
0e352963fd
Emit series of conditionals with &&, emitting stuff like this:
...
if (N1.getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
!CodeGenMap.count(N1.getValue(0)) &&
!CodeGenMap.count(N1.getValue(1))) {
instead of this:
if (N1.getOpcode() == ISD::LOAD) {
if (N1.hasOneUse()) {
if (!CodeGenMap.count(N1.getValue(0))) {
if (!CodeGenMap.count(N1.getValue(1))) {
llvm-svn: 25763
2006-01-29 04:41:05 +00:00
7c0149d1d6
Factor matching code that is common between patterns. This works around
...
GCC not jump-threading across this common code, and produces far nicer
output.
llvm-svn: 25762
2006-01-29 04:25:26 +00:00
d3a63de91e
Split out code generation from analysis from emission
...
llvm-svn: 25759
2006-01-29 02:57:39 +00:00
afe9baeb69
move some code around, no change in the generated code
...
llvm-svn: 25758
2006-01-29 02:43:35 +00:00
5255c6c627
now that we have control over emission of the code, emit the code using nested
...
"if" statements (indenting it appropriately, of course) instead of using goto's.
This inverts the logic for all of the if statements, which makes things simpler
to understand in addition to making the generated code easier to read.
llvm-svn: 25757
2006-01-28 20:43:52 +00:00
4c4da201bf
Change PatternCodeEmitter to emit code into a buffer instead of emitting it
...
directly to the output file. This makes things simple because the code doesn't
have to worry about indentation or the case when there is no goto. It also
allows us to indent the code better without touching everything :)
llvm-svn: 25756
2006-01-28 20:31:24 +00:00
4bfd3b40b0
Make long warnings wrap and have less indent so other portions of the page
...
are not skewed out of view.
llvm-svn: 25753
2006-01-28 19:44:48 +00:00
a7d6bbff00
Fit to 80 columns, no functionality change
...
llvm-svn: 25752
2006-01-28 19:06:51 +00:00
e251e92c23
Teach tablegen to generate code that is VC++ warning-free.
...
llvm-svn: 25709
2006-01-27 22:22:28 +00:00
e555a92c8d
(store (op (load ...)), ...)
...
If store's chain operand is load, then use load's chain operand instead. If
it isn't (likely a TokenFactor), then do not allow the folding.
llvm-svn: 25708
2006-01-27 22:13:45 +00:00
d98701c639
Subtarget feature can now set any variable to any value
...
llvm-svn: 25678
2006-01-27 08:09:42 +00:00
4d5a93ed28
Use printInlineAsm to, well, print inline asm's.
...
llvm-svn: 25677
2006-01-27 02:10:50 +00:00
543fe4b6aa
PHI and INLINEASM are now builtin instructions provided by Target.td
...
llvm-svn: 25673
2006-01-27 01:45:06 +00:00
db2a5f09f1
If we want to emit things in enum order, use getInstructionsByEnumValue to
...
get the order, don't compute it ourselves.
Don't emit stuff like (14<<0), emit 14 instead.
Don't attempt to get target properties for builtin instructions.
llvm-svn: 25672
2006-01-27 01:44:09 +00:00
ac8b13b32b
There is at least a 'noitinerary' itinerary now
...
llvm-svn: 25671
2006-01-27 01:41:55 +00:00
ec249a3d30
Don't emit JIT code for these instructions
...
llvm-svn: 25669
2006-01-27 01:39:38 +00:00
5815669251
Teach the dag selectors to select InlineAsm nodes.
...
Aren't we happy the pattern selectors are almost all gone?
llvm-svn: 25666
2006-01-26 23:08:55 +00:00
e9025f1f3b
Another folding problem: if a node r/w chain or flag, don't fold it if it
...
has already been selected. The number of use check is not strong enough since
a node can be replaced with newly created target node. e.g. If the original
node has two uses, when it is selected for one of the uses it is replaced with
another. Each node now has a single use but isel still should not fold it.
llvm-svn: 25651
2006-01-26 19:13:45 +00:00
dc8365d4f3
Add a FIXME comment.
...
llvm-svn: 25635
2006-01-26 02:13:31 +00:00
ecfaa0a1c9
Incoming (and optional) flag bugs. They may be embedded inside a inner node of
...
a pattern. Also, nodes which take incoming flag should not be folded if it has
more than one use.
llvm-svn: 25627
2006-01-26 00:22:25 +00:00
c5c228fa59
Fix an optional in flag bug.
...
llvm-svn: 25590
2006-01-24 20:46:50 +00:00
295e196558
Optional InFlag was not being included in node.
...
llvm-svn: 25588
2006-01-24 20:07:38 +00:00
e272b4ec17
Prevent folding of a node with multiple uses if the node already folds a load!
...
Here is an example where the load ended up being done twice:
%A = global uint 0
uint %test(uint %B, ubyte %C) {
%tmp = load uint *%A;
%X = shl uint %tmp, ubyte %C
%Cv = sub ubyte 32, %C
%Y = shr uint %B, ubyte %Cv
%Z = or uint %Y, %X
store uint %Z, uint* %A
ret uint %Z
}
==>
subl $4, %esp
movl %ebx, (%esp)
movl 8(%esp), %edx
movl A, %eax
movb 12(%esp), %bl
movb %bl, %cl
shldl %cl, %edx, %eax
movb %bl, %cl
shldl %cl, %edx, A
movl (%esp), %ebx
addl $4, %esp
ret
llvm-svn: 25471
2006-01-20 01:11:03 +00:00
823a00a8b5
Don't include generated lexer .cpp files.
...
llvm-svn: 25466
2006-01-19 22:01:51 +00:00
9e7fb7b2fc
Bug fix. Flag operand number may be calculated incorrectly.
...
llvm-svn: 25465
2006-01-19 21:57:10 +00:00
a15731cd50
Use pattern information to determine whether the use expects this
...
instruction to produce a result. e.g MUL8m, the instruction does not
produce a explicit result. However it produces an implicit result in
AL which would be copied to a temp. The root operator of the matching
pattern is a mul so the use would expect it to produce a result.
llvm-svn: 25458
2006-01-19 10:12:58 +00:00
acec02ebf5
Prevent unnecessary CopyToReg when the same HW register appears in two spots
...
in the pattern.
llvm-svn: 25437
2006-01-19 01:55:45 +00:00
dce31c8d70
fix a broken comment
...
llvm-svn: 25411
2006-01-17 21:31:18 +00:00
5ed803256d
Regenerated the Lex and Yacc output files on Linux. It seems that our
...
Linux machines don't like the source code generated on MacOS X for some
reason.
llvm-svn: 25394
2006-01-17 17:01:34 +00:00
61864ec3fe
Emit a type matching check for ComplexPatterns.
...
llvm-svn: 25392
2006-01-17 07:36:41 +00:00
a039d439dc
Type inferencing bug
...
llvm-svn: 25337
2006-01-15 10:04:45 +00:00
bd1de84121
Allow transformation from GlobalAddress to TargetGlobalAddress and
...
ExternalSymbol to TargetExternalSymbol.
llvm-svn: 25252
2006-01-12 19:35:54 +00:00
e6300aaabc
GlobalAddress -> TargetGlobalAddress; ExternalSymbol -> TargetExternalSymbol
...
llvm-svn: 25245
2006-01-12 07:54:57 +00:00
31686087cd
Some minor fixes.
...
llvm-svn: 25227
2006-01-11 22:16:13 +00:00
e18ad392d3
Always select target registers to themselves
...
llvm-svn: 25218
2006-01-11 19:52:27 +00:00
3857f6d067
Emit an error instead of an assertion if trying to do bogus things in result patterns.
...
llvm-svn: 25194
2006-01-11 01:33:49 +00:00
230044839d
Added support for the extractelement operation.
...
llvm-svn: 25181
2006-01-10 19:05:34 +00:00
4b0623e141
* Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag and
...
SNDPOutFlag to DAG nodes. These properties do not belong to target specific
instructions.
* Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's
optional. Used by ret / call, etc.
llvm-svn: 25154
2006-01-09 18:27:06 +00:00
482ef91d26
Pattern complexity calculation fix.
...
llvm-svn: 25133
2006-01-06 22:19:44 +00:00
46634d21e3
Tweak pattern complexity calc.
...
llvm-svn: 25122
2006-01-06 02:30:23 +00:00
6b037909ff
Bug fix wrt chain operand.
...
llvm-svn: 25115
2006-01-06 00:41:12 +00:00
a69bb989f1
Replace fix with one less disruptive to the original code.
...
Also note that GCC 4.1 also correctly flags the syntax error.
llvm-svn: 25076
2006-01-04 03:23:30 +00:00
7d17a6bc86
Tblgen was generating syntactically illegal C++ code like:
...
SDOperand Tmp0,Tmp1,Tmp2,Tmp3,;
GCC has a bug (24907) in which is fails to catch this, but VC++ correctly
notes its illegality, so tblgen must be taught to only generate legal C++.
llvm-svn: 25075
2006-01-04 03:15:19 +00:00
3d38031bef
Remove obsolete comment, make things look a bit nicer
...
llvm-svn: 25070
2006-01-04 00:32:01 +00:00
c29793a077
reduce stack usage of the recursive SelectCode function by out-lining each
...
case of the switch statement into its own method.
llvm-svn: 25069
2006-01-04 00:25:00 +00:00
81e4dbc6a1
Remove my previous ugly hack that tries to reduce the stack space usage
...
of SelectCode to make way for a better solution.
llvm-svn: 25068
2006-01-03 22:55:16 +00:00
def44bec82
HP-UX DVDs are crunchy and good to eat
...
llvm-svn: 25052
2005-12-30 16:41:48 +00:00
018da4f5ef
almost got the HP-UX tester up.. :)
...
llvm-svn: 25051
2005-12-30 14:56:37 +00:00
336dba6fb1
Add support for generating v4i32 altivec code
...
llvm-svn: 25046
2005-12-30 00:12:56 +00:00
ccb1aebcd3
This gets most of the backends building with HP HappyC++.
...
llvm-svn: 25029
2005-12-27 10:56:22 +00:00
14c53b45f5
Added field noResults to Instruction.
...
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
llvm-svn: 25017
2005-12-26 09:11:45 +00:00
14492afc23
more standards-compliance stuff
...
llvm-svn: 25014
2005-12-26 05:08:55 +00:00
0dc12c38e5
support targetexternalsym
...
llvm-svn: 25005
2005-12-24 23:36:59 +00:00
72aaf8e374
* Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAG
...
support which is fragile.
* Fixed a number of bugs.
llvm-svn: 24996
2005-12-23 22:11:47 +00:00
d834d495b2
silence some bogus gcc warnings
...
llvm-svn: 24962
2005-12-22 20:37:36 +00:00
a87d743912
Attempt to fix a crash on WIN32.
...
llvm-svn: 24936
2005-12-22 02:35:21 +00:00
991bc6d6ba
* Added support for FLAG - a special nameless flag register. Can be used as
...
either an operand or a result.
* Fixed some more flag / chain bugs.
llvm-svn: 24933
2005-12-22 02:24:50 +00:00
f646926ecf
Allows instructions which no explicit operands. e.g. X86 RET which has but
...
an implicit flag operand.
llvm-svn: 24916
2005-12-21 20:20:49 +00:00
812a56e888
Eliminate some GCC warnings from the generated code
...
llvm-svn: 24897
2005-12-21 05:31:05 +00:00
4bf64a8ba4
Fix the semantic of Requires<[cond]> to mean if (!cond) goto PXXFail;
...
llvm-svn: 24883
2005-12-20 20:08:01 +00:00
777bb6eb45
This ugly patch works around a GCC bug where it is compiling SelectCode to
...
use too much stack space, overflowing the stack for large functions. Instead
of emitting new SDOperands in each match block, we emit some common ones at
the top of SelectCode then reuse them when possible.
This reduces the stack size of SelectCode from 28K to 21K. Note that GCC
compiles it to 512 bytes :-/
I've filed GCC PR 25505 to track this.
llvm-svn: 24882
2005-12-20 19:41:03 +00:00
9696f63d3e
Now support instructions with implicit write to non-flag registers.
...
llvm-svn: 24878
2005-12-20 07:37:41 +00:00
2dd7e06d8e
Added a break that I meant to include originally, for efficiency. Basically
...
it keeps it from trying to add the same node to the node set
over and over if it matches multiple given patterns. Also in cases where there
are a lot of patterns to be matched, and it matches an early one, this
will make the script run slightly faster. It's more there because it logically
should be, than anything else, I mean, Python is never going to be fast ;-)
llvm-svn: 24876
2005-12-20 02:03:23 +00:00
fe90b604a4
Lefted out a fix in the previous check in.
...
llvm-svn: 24873
2005-12-20 00:06:17 +00:00
19b9f15377
Fix another bug related to chain / flag.
...
llvm-svn: 24868
2005-12-19 22:40:04 +00:00
9bd85c2f19
Fixes for a number of bugs: save flag results in CodeGenMap, folded chains
...
may not all have ResNo == 0.
llvm-svn: 24858
2005-12-19 07:18:51 +00:00
136f465fa2
This is a script to extract nodes and edges associated with those nodes
...
from a dot file that is the output of DSA. Nodes to extract
are specified by giving the name of the node seen in the graphical
representation, i.e. in the .ps if the node is specified %xyz
asking for just x, xy, or xyz will retain it in the output file.
Because it operates on substrings underspecifying may result
in additional unexpected nodes. Be as specific as possible.
Obviously, however, if you ask for %xyz and there is a
getelementptr of %xyz you will get both nodes. Some manual
editing may still be necessary because of this, but this script
can pare down 10,000 line files to 20 line files, making like easier.
llvm-svn: 24851
2005-12-19 01:23:31 +00:00
f7ae0a95fe
Handle basic block nodes
...
llvm-svn: 24833
2005-12-18 21:05:44 +00:00
abb11cc83e
More fixes for Selection of copyto/fromreg with a flag
...
llvm-svn: 24829
2005-12-18 15:45:51 +00:00
fc3d4f8fd8
Select copytoreg and copyfromreg nodes that have flag operands correctly.
...
llvm-svn: 24827
2005-12-18 15:28:25 +00:00
e22f9181f7
Support for read / write from explicit registers with FlagVT type.
...
llvm-svn: 24753
2005-12-17 01:19:28 +00:00
d296a43f96
Added support to specify predicates.
...
llvm-svn: 24715
2005-12-14 22:02:59 +00:00
6a31777c8e
Skip over srcvalue nodes when generating ISEL code.
...
llvm-svn: 24704
2005-12-14 02:21:57 +00:00
6148153230
Bug fix: CodeGenMap[N] = ... -> CodeGenMap[N.getValue(0)] = ...
...
llvm-svn: 24680
2005-12-12 23:45:21 +00:00
7e4c01eee3
At top of generated isel SelectCode() is this:
...
if (!N.Val->hasOneUse()) {
std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(N);
if (CGMI != CodeGenMap.end()) return CGMI->second;
}
Suppose a DAG like this:
X
^ ^
/ \
USE1 USE2
Suppose USE1 is being selected first and during which X is selected and
returned a new node. After this, USE1 is no longer an use of X. During USE2
selection, X will be selected again since it has only one use!
The fix is to always query CodeGenMap.
llvm-svn: 24679
2005-12-12 23:22:48 +00:00
cdb16ef6f3
Bug fix: finding the correct incoming chain for pattern with nested src operand. And a minor change to make output code slightly more readible.
...
llvm-svn: 24669
2005-12-12 19:37:43 +00:00
08dbd94632
Send an indicator to llvm-testresults if the build failed
...
llvm-svn: 24665
2005-12-11 19:55:39 +00:00
4e56db674c
Add support for TargetConstantPool nodes to the dag isel emitter, and use
...
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
llvm-svn: 24657
2005-12-10 02:36:00 +00:00
0da396ffe2
Stop emitting a redudant type check for complex pattern node.
...
llvm-svn: 24655
2005-12-10 01:57:33 +00:00
bac252c289
For instructions which produce no result, e.g. store, chain's Resno == 0.
...
llvm-svn: 24652
2005-12-10 00:09:17 +00:00
433573f4c6
Add a new SDTCisPtrTy constraint, which indicates that an operand must have
...
the same type as the pointer type for a target.
llvm-svn: 24649
2005-12-09 22:57:42 +00:00
499ab2a9fa
* Do not allow nodes which produce chain results (e.g. loads) to be folded if
...
it has more than one real use (non-chain uses).
* Record folded chain producing node in CodeGenMap.
* Do not fold a chain producing node if it has already been selected as an
operand of a chain use.
llvm-svn: 24647
2005-12-09 22:45:35 +00:00
c1f911a238
Prevent folding of instructions which produce chains that have more than 1 real use
...
llvm-svn: 24643
2005-12-09 06:06:08 +00:00
f423a17e33
* Make sure complex pattern operands are selected first since their select
...
functions can return false and causing the instruction pattern match to fail.
* Code clean up.
llvm-svn: 24642
2005-12-09 00:48:42 +00:00
c9a620060b
* Added an explicit type field to ComplexPattern.
...
* Renamed MatchingNodes to RootNodes.
llvm-svn: 24636
2005-12-08 02:14:08 +00:00
9b9567bfb5
Added support for ComplexPattern. These are patterns that require C++ pattern
...
matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4.
llvm-svn: 24634
2005-12-08 02:00:36 +00:00
0fe76d1585
* Infer instruction property hasCtrlDep from pattern if it has one.
...
* Fixed a bug related to hasCtrlDep property use.
llvm-svn: 24610
2005-12-05 23:08:55 +00:00
ba369ae8f1
Implement PR673: for explicit register references, use type information
...
if available
llvm-svn: 24597
2005-12-05 02:36:37 +00:00
3717b4c830
Add some methods
...
llvm-svn: 24596
2005-12-05 02:35:08 +00:00
d49489f01e
Generate code to silence bogus GCC warnings.
...
llvm-svn: 24593
2005-12-05 00:48:51 +00:00
f02bb9af8b
* Commit the fix (by Chris) for a tblgen type inferencing bug.
...
* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.
llvm-svn: 24587
2005-12-04 08:18:16 +00:00
006bb04f3a
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
...
work. This change has no effect on generated code.
llvm-svn: 24563
2005-12-01 04:51:06 +00:00
fed83adbe3
Teach tblgen to accept register source operands in patterns, e.g.
...
def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
"shl{b} {%cl, $dst|$dst, %CL}",
[(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>;
This generates a CopyToReg operand and added its 2nd result to the shl as
a flag operand.
llvm-svn: 24557
2005-12-01 00:18:45 +00:00
faad542d24
Nuke CodeGenInstruction's ValueType member, it is no longer used.
...
llvm-svn: 24556
2005-12-01 00:12:04 +00:00
cdf2c67888
Stop checking the ValueType of the CodeGenInstruction. Instead, use the
...
ValueType from the RegisterClass or Operands. This step is necessary to
allow RegisterClasses to have multiple ValueTypes.
llvm-svn: 24555
2005-12-01 00:06:14 +00:00
e479ccb27b
fit into 80 columns
...
llvm-svn: 24554
2005-11-30 23:58:18 +00:00
3e63dc00da
Make the code generated by tblgen return the result of SelectNodeTo, to
...
permit future changes.
llvm-svn: 24553
2005-11-30 23:08:45 +00:00
6f8c1ace6e
No longer track value types for asm printer operands, and remove them as
...
an argument to every operand printing function. Requires some slight
tweaks to x86, the only user.
llvm-svn: 24541
2005-11-30 18:54:35 +00:00
f621b333f3
Fix some copy and paste typos.
...
llvm-svn: 24540
2005-11-30 18:37:14 +00:00
c8af0cb893
Better error message when unrecognized opcode is seen.
...
llvm-svn: 24519
2005-11-29 18:44:58 +00:00
4d0251ad55
Add the new vector types to tablegen
...
llvm-svn: 24514
2005-11-29 06:19:38 +00:00
f2807be3da
Initialize this variable on all paths, fixing a crasher in windows. Thanks
...
to JeffC for pointing this out.
llvm-svn: 24426
2005-11-19 07:48:33 +00:00
6bc0304c91
Teach tblgen about instruction operands that have multiple MachineInstr
...
operands, digging into them to find register values (used on X86). Patch
by Evan Cheng!
llvm-svn: 24424
2005-11-19 07:05:57 +00:00
a70c7dff2e
Validate that the input to 'Pat' patterns is sane.
...
llvm-svn: 24393
2005-11-17 17:43:52 +00:00
2a230e1c1a
teach tblgen to be smart enough to handle tglobaladdr nodes
...
llvm-svn: 24391
2005-11-17 07:39:45 +00:00
b22950df6c
fix a tblgen bug that Evan ran into, where we would lose the '$src' name
...
on patterns like "(set R32:$dst, (i32 imm:$src))"
llvm-svn: 24383
2005-11-16 23:14:54 +00:00
3ea1e255f7
remove these labels, there are now bigger jumps in the graph that are unlabeled
...
llvm-svn: 24365
2005-11-15 06:44:15 +00:00
d6d3afb05e
1. Remove ranges from itinerary data.
...
2. Tidy up the subtarget emittined code.
llvm-svn: 24172
2005-11-03 22:47:41 +00:00
64209fd14b
Reject integer literals that are out of range for their type.
...
llvm-svn: 24162
2005-11-03 05:46:11 +00:00
590176be16
Add support for immediates directly in the pattern, this allows itanium to
...
define:
def : Pat<(i1 1), (CMPEQ r0, r0)>;
llvm-svn: 24149
2005-11-02 06:49:14 +00:00
802748cd61
Allow itineraries to be passed through the Target Machine.
...
llvm-svn: 24139
2005-11-01 20:06:59 +00:00
9e1784d738
Keep VC++ happy.
...
llvm-svn: 24137
2005-11-01 18:04:06 +00:00
1deb86dbf4
Let people who run the nightly tester specify paths to external tests, instead
...
of having to hack the nightly tester script itself.
as an example, I use the following for my machine:
$HOME/llvm/utils/NightlyTest.pl -parallel -release -enable-llcbeta \
-spec2000path /Volumes/ProjectsDisk/cvs/benchmarks/speccpu2000-llvm/benchspec/ \
-povraypath /Volumes/ProjectsDisk/cvs/benchmarks/povray31 \
-namdpath /Volumes/ProjectsDisk/cvs/benchmarks/namd
llvm-svn: 24136
2005-11-01 17:59:42 +00:00
0433df136f
Emit itinerary class in instruction info.
...
llvm-svn: 24122
2005-10-31 17:16:46 +00:00
3763a50d82
Generate cpu to itinerary map.
...
llvm-svn: 24121
2005-10-31 17:16:01 +00:00
af6b34ff44
Revert an accidental commit.
...
llvm-svn: 24098
2005-10-29 17:01:41 +00:00
d91df9d941
Make negative immediates in patterns work correctly, silence some warnings
...
building the itanium backend.
llvm-svn: 24095
2005-10-29 16:39:40 +00:00
742606ad30
Switch more code over to using getValueAsListOfDefs. Look at all the -'s. :)
...
llvm-svn: 24074
2005-10-28 22:59:53 +00:00
7ad0bed89f
Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accurately
...
reflect what it is.
Convert some more code over to use it.
llvm-svn: 24072
2005-10-28 22:49:02 +00:00
802bd8d94f
Use the new interface Jim added
...
llvm-svn: 24071
2005-10-28 22:43:25 +00:00
dffe5978a3
Removed Mr. Smith from the code.
...
llvm-svn: 24070
2005-10-28 21:47:29 +00:00
b04feb633f
Added method to return a vector of records for a ListInit of Def field. This
...
simplifies using list of records.
llvm-svn: 24069
2005-10-28 21:46:31 +00:00
db53c998de
The nightly tester report doesn't report JIT code size anymore, remove it
...
from the olden graph.
llvm-svn: 24057
2005-10-28 16:35:18 +00:00
1959575208
Add some commentary.
...
llvm-svn: 24055
2005-10-28 15:20:43 +00:00
b0aa47b043
Keep Visual Studio happy.
...
llvm-svn: 24052
2005-10-28 01:43:09 +00:00
86f002cc32
Now generating instruction itineraries for scheduling. Not my best work, but...
...
llvm-svn: 24050
2005-10-27 19:47:21 +00:00
777a26efc3
Simplify.
...
llvm-svn: 24015
2005-10-26 17:49:21 +00:00
a2b5235fac
Give full control of subtarget features over to table generated code.
...
llvm-svn: 24013
2005-10-26 17:30:34 +00:00
f277ac7caa
Condcodes are in the ISD namespace
...
llvm-svn: 24010
2005-10-26 17:02:02 +00:00
611b0c634c
Add support for CondCode's
...
llvm-svn: 24008
2005-10-26 16:59:37 +00:00
d980c46f52
Emit some boilerplate for targets
...
llvm-svn: 23983
2005-10-25 20:35:14 +00:00
1b7369b1ae
Refactored to make room for more stuff (scheduling info.)
...
llvm-svn: 23975
2005-10-25 15:16:36 +00:00
fc9f5773d0
Fix an incompatibility with GCC 4.1, thanks to Vladimir Merzliakov
...
for pointing this out!
llvm-svn: 23963
2005-10-24 15:04:15 +00:00
4f48e67c6c
Add the needed #include, emit enums with the sizes of tables, remove
...
definitions from the LLVM namespace, since they are all static.
llvm-svn: 23907
2005-10-23 22:33:08 +00:00
49f7b69997
Remove the obsolete instr selector emitter
...
llvm-svn: 23894
2005-10-23 05:47:52 +00:00
a1beea6c7d
Sort the features and processor lists for the sake of search (and maintainers.)
...
llvm-svn: 23879
2005-10-22 07:59:56 +00:00
9ed9032e22
Plugin new subtarget backend into the build.
...
llvm-svn: 23870
2005-10-21 19:05:19 +00:00
cfda85ad91
New TableGen backends for subtarget information. Only command line stuff
...
active now. Scheduling itinerary next.
llvm-svn: 23869
2005-10-21 19:00:04 +00:00
8bda5afd91
Make tblgen emit:
...
tblgen: In ZAPNOTi: Cannot use 'IZAPX' in an input pattern!
for a bad pattern, instead of an ugly assertion.
llvm-svn: 23854
2005-10-21 01:19:59 +00:00
c9ad735e78
add support for literal immediates in patterns to match, allowing us to
...
write things like this:
def : Pat<(add GPRC:$in, 12),
(ADD12 GPRC:$in)>;
Andrew: if this isn't enough or doesn't work for you, please lemme know.
llvm-svn: 23819
2005-10-19 04:41:05 +00:00
7f6f565846
Add basic support for integer constants in pattern results.
...
llvm-svn: 23817
2005-10-19 04:30:56 +00:00
2ae2f99326
Fix some checking that was causing duraid to get a perplexing assertion
...
instead of a happy error message
llvm-svn: 23816
2005-10-19 04:12:14 +00:00
b8014e10ae
Add support for patterns that have physical registers in them. Testcase:
...
def : Pat<(trunc G8RC:$in),
(OR8To4 G8RC:$in, X0)>;
Even though this doesn't make any sense on PPC :)
llvm-svn: 23815
2005-10-19 02:07:26 +00:00
c8f899f98d
Asserting here is to violent
...
llvm-svn: 23814
2005-10-19 01:55:23 +00:00
8baf5043a8
Nate wants to define 'Pat's which turn into instructions that don't have
...
patterns. Certainly a logical request.
llvm-svn: 23810
2005-10-19 01:27:22 +00:00
ed653cbe43
Duraid pointed out that it is impolite to emit PPC:: into the IA64 backend
...
llvm-svn: 23780
2005-10-18 04:41:01 +00:00
825298b060
Make the generated code significantly more memory efficient, by using
...
SelectNodeTo instead of getTargetNode when possible.
llvm-svn: 23758
2005-10-16 01:41:58 +00:00
6b22d2554a
Implement the last major missing piece in the DAG isel generator: when emitting
...
a pattern match, make sure to emit the (minimal number of) type checks that
verify the pattern matches this specific instruction. This allows FMA32
patterns to not match double expressions for example.
llvm-svn: 23748
2005-10-15 21:34:21 +00:00
c4db8f4163
Now that we have int/fp lattice values, implement the SDTCisOpSmallerThanOp
...
type constraint. This lets tblgen realize that it doesn't need any dynamic
type checks for fextend/fround on PPC (and many other targets), because there
are only two fp types.
llvm-svn: 23730
2005-10-14 06:25:00 +00:00
ecaf56b21a
Fairly serious rework of the typing code to add new int/fp lattice values.
...
Overall, no functionality change yet though.
llvm-svn: 23729
2005-10-14 06:12:03 +00:00
cdf483556f
simplify the code a bit
...
llvm-svn: 23728
2005-10-14 05:08:37 +00:00
4892df38f3
Add basic support for recognizing a new SDTCisOpSmallerThanOp type constraint
...
llvm-svn: 23725
2005-10-14 04:53:53 +00:00
7b0275ba8c
Implement a couple of new (important) features.
...
1. If an operation has to be int or fp and the target only supports one
int or fp type, relize that the op has to have that type.
2. If a target has operations on multiple types, do not emit matching code
for patterns involving those operators, since we do not emit the code to
check for them yet. This prevents PPC from generating FP ops currently.
Also move some code around into more logical places.
llvm-svn: 23724
2005-10-14 04:11:13 +00:00
90c5b9c83c
Do not let getLegalValueTypes return a list with duplicates in it
...
llvm-svn: 23723
2005-10-14 03:54:49 +00:00
16fe45c91b
Updated to be less restrictive on what is matched
...
llvm-svn: 23712
2005-10-13 17:31:30 +00:00
e70b0d37c3
apparently one of the makefile changes changed libprofile.so to profile.so
...
llvm-svn: 23709
2005-10-13 16:34:24 +00:00
fd377d9033
This script is used to remove nodes with the label %tmp(.#)* and all
...
edges associated with said node from the dot files produced by
DSA.
llvm-svn: 23708
2005-10-13 16:26:50 +00:00
e51d6a9f70
put the right labels on the data
...
llvm-svn: 23599
2005-10-02 21:51:38 +00:00
d4ff3c1324
Emit the value type for each register class.
...
llvm-svn: 23584
2005-10-02 06:23:37 +00:00
c9f4219cfc
Rename MRegisterDesc -> TargetRegisterDesc for consistency
...
llvm-svn: 23564
2005-09-30 17:49:27 +00:00
3e020bb619
remove some more initializers
...
llvm-svn: 23562
2005-09-30 17:41:05 +00:00
ddc69bbbba
trim down the target info structs now that we have a preferred spill register class for each callee save register
...
llvm-svn: 23560
2005-09-30 17:35:22 +00:00
da6fcc9f49
Compute a preferred spill register class for each callee-save register
...
llvm-svn: 23553
2005-09-30 06:44:45 +00:00
26f5fb1277
Fix a warning
...
llvm-svn: 23550
2005-09-30 06:09:50 +00:00
1916ef75cf
Regenerate
...
llvm-svn: 23549
2005-09-30 04:53:25 +00:00
b509577605
Refactor this a bit to move ParsingTemplateArgs to only apply to classes,
...
not defs.
Implement support for forward definitions of classes. This implements
TableGen/ForwardRef.td.
llvm-svn: 23548
2005-09-30 04:53:04 +00:00
20b0e3cee4
Regenerate
...
llvm-svn: 23546
2005-09-30 04:42:56 +00:00
ad61925e27
Generate a parse error instead of a checked exception if template args are
...
used on a def.
llvm-svn: 23545
2005-09-30 04:42:31 +00:00
6e60c8fe05
regenerate
...
llvm-svn: 23543
2005-09-30 04:11:27 +00:00
e04e1384fc
Refactor the grammar a bit to implement TableGen/ForwardRef.td
...
llvm-svn: 23542
2005-09-30 04:10:49 +00:00
2a6fd61dfc
allow regs to be in multiple reg classes
...
llvm-svn: 23540
2005-09-30 01:33:48 +00:00
366fe04301
Teach tablegen to reassociate operators when possible. This allows it to
...
find all of teh pattern matches for EQV from one definition
llvm-svn: 23529
2005-09-29 22:36:54 +00:00
e86824e57a
Teach tblgen to build permutations of instructions, so that the target author
...
doesn't have to specify them manually. It currently handles associativity,
e.g. knowing that (X*Y)+Z also matches X+(Y*Z) and will be extended in
the future.
It is smart enough to not introduce duplicate patterns or patterns that can
never match.
llvm-svn: 23526
2005-09-29 19:28:10 +00:00
492e70f4ec
add support for an associative marker
...
llvm-svn: 23502
2005-09-28 20:58:06 +00:00
8bb25cd68a
Emit an error if instructions or patterns are defined but can never match.
...
Currently we check that immediate values live on the RHS of commutative
operators. Defining ORI like this, for example:
def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
"ori $dst, $src1, $src2",
[(set GPRC:$dst, (or immZExt16:$src2, GPRC:$src1))]>;
results in:
tblgen: In ORI: Instruction can never match: Immediate values must be on the RHS of commutative operators!
llvm-svn: 23501
2005-09-28 19:27:25 +00:00
f74c30c281
collect commutativity information
...
llvm-svn: 23499
2005-09-28 18:28:29 +00:00
3622f15491
Prefer cheaper patterns to more expensive ones. Print the costs to the generated
...
file
llvm-svn: 23492
2005-09-28 17:57:56 +00:00
75b4c5d868
Select Constant nodes to TargetConstant nodes
...
llvm-svn: 23488
2005-09-28 16:58:06 +00:00
d455c36c91
memoize the assert results
...
llvm-svn: 23457
2005-09-26 22:10:24 +00:00
c9153266c6
Emit the switch stmt cases in alphabetical order instead of pointer order,
...
which is not stable.
llvm-svn: 23456
2005-09-26 21:59:35 +00:00
d5de8544f8
implement a fixme: only select values once, even if used multiple times.
...
llvm-svn: 23454
2005-09-26 21:53:26 +00:00
23b1d28e69
Fix VC++ build errors.
...
llvm-svn: 23431
2005-09-25 19:04:43 +00:00
cc1d38160d
memoize translations
...
llvm-svn: 23419
2005-09-24 00:50:51 +00:00
0afb14cade
Teach the DAG isel generator to emit code that creates nodes.
...
Fix a few corner cases parsing things like (i32 imm:$foo)
llvm-svn: 23417
2005-09-24 00:40:24 +00:00
cd093e868e
Emit better code (no more copies for var references), and support DAG patterns
...
(e.g. things like rotates).
llvm-svn: 23416
2005-09-23 23:16:51 +00:00
8ffb99b4fe
Fix a fixme by passing around SDOperand's instead of SDNode*'s
...
llvm-svn: 23415
2005-09-23 21:53:45 +00:00
cc8a564cb1
Emit code that matches the incoming DAG pattern and checks predicates.
...
This does not check that types match yet, but PPC only has one integer type
;-).
This also doesn't have the code to build the resultant dag.
llvm-svn: 23414
2005-09-23 21:33:23 +00:00
323a47970e
emit information about the order patterns are to be matched.
...
llvm-svn: 23413
2005-09-23 20:52:47 +00:00
abb430bad2
start filling in the switch stmt
...
llvm-svn: 23412
2005-09-23 19:36:15 +00:00
7884fffb00
Fix a minor bug, add comments
...
llvm-svn: 23370
2005-09-16 00:29:46 +00:00
59e96143a2
teach the type inference code how to infer types for instructions and node
...
xforms. Run type inference on result patterns, so we always have fully typed
results (and to catch errors in .td files).
llvm-svn: 23369
2005-09-15 22:23:50 +00:00
fedd9a5e1d
put instructions into a map instead of a vector for quick lookup
...
llvm-svn: 23368
2005-09-15 21:57:35 +00:00
f38ce8f756
when parsing instructions remember information about the types taken and
...
returned.
llvm-svn: 23367
2005-09-15 21:51:12 +00:00
a0a986c9ae
Start parsing "Pattern" nodes
...
llvm-svn: 23365
2005-09-15 21:42:00 +00:00
f79ad4cb32
rename a couple of methods, add structure for pattern parsing
...
llvm-svn: 23364
2005-09-15 02:38:02 +00:00
a155256a71
Verify that xform functions only occur in logical places
...
llvm-svn: 23363
2005-09-14 23:05:13 +00:00
Chris Lattner