4 Commits

Author	SHA1	Message	Date
Jay Foad	590964c835	[AMDGPU] More accurate gfx10 latencies ... Differential Revision: https://reviews.llvm.org/D81012	2020-06-04 10:29:32 +01:00
Matt Arsenault	69999605ee	GlobalISel: Move code into lowering for G_MERGE_VALUES ... Currently this code exists in widenScalar for G_MERGE_VALUE sources. I'm not sure if the existing expansion in widenScalar should be removed or not. The widenScalar variant tries to extend to the requested size, but this just uses the original bitwidth.	2020-05-09 16:39:37 -04:00
Matt Arsenault	0b46b078b6	AMDGPU/GlobalISel: Fix incorrect VOP3P fneg folding ... We use some s32 values in VOP3P operands, and won't see any intervening casts from a 32-bit fneg. Make sure it's really a packed fneg before folding.	2020-02-24 21:20:35 -05:00
Matt Arsenault	db06870dbd	AMDGPU: Move dot intrinsic patterns to instruction def ... I tried to use some of the new tablegen features to avoid creating different operand list permutations, but I still don't see a way to programmatically build a source pattern dag. Also add GlobalISel tests, which now all import successfully. Some of the fneg fold tests are incorrect, which need to be fixed in a future commit	2020-02-21 13:35:40 -05:00