llvm-project

Commit Graph

Author	SHA1	Message	Date
Matt Arsenault	f9a42ed0a7	AMDGPU: Relax 32-bit SGPR register class Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This will allow the register coalescer to do a better job eliminating copies to m0. For GlobalISel, as a terrible hack, use SGPR_32 for things that should use SCC until booleans are solved. llvm-svn: 375267	2019-10-18 18:26:37 +00:00
Matt Arsenault	77e3e9cafd	AMDGPU/GlobalISel: Select llvm.amdgcn.class Also fixes missing SubtargetPredicate on f16 class instructions. llvm-svn: 371436	2019-09-09 18:29:45 +00:00

Author

SHA1

Message

Date

Matt Arsenault

f9a42ed0a7

AMDGPU: Relax 32-bit SGPR register class

Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This
will allow the register coalescer to do a better job eliminating
copies to m0.

For GlobalISel, as a terrible hack, use SGPR_32 for things that should
use SCC until booleans are solved.

llvm-svn: 375267

2019-10-18 18:26:37 +00:00

Matt Arsenault

77e3e9cafd

AMDGPU/GlobalISel: Select llvm.amdgcn.class

Also fixes missing SubtargetPredicate on f16 class instructions.

llvm-svn: 371436

2019-09-09 18:29:45 +00:00

2 Commits