Eli Friedman
4028a51c74
Fix test; sorry for any inconvenience.
...
llvm-svn: 138966
2011-09-01 21:25:42 +00:00
Eli Friedman
71f5c2f158
Fix an issue with the IR sink pass found by inspection. (I'm not sure anyone is actually using this, but might as well fix it since I found the issue.)
...
llvm-svn: 138965
2011-09-01 21:21:24 +00:00
Eli Friedman
cc6e92892f
Add missing newline.
...
llvm-svn: 138964
2011-09-01 21:20:11 +00:00
Benjamin Kramer
c032617581
XFAIL this test on arm until the backend is fixed.
...
llvm-svn: 138955
2011-09-01 18:40:03 +00:00
Benjamin Kramer
0f6ff8cb2b
This test depends on cmov being available.
...
llvm-svn: 138954
2011-09-01 18:40:01 +00:00
Jakob Stoklund Olesen
5dc87d0f4d
Permit remat of partial register defs when it is safe.
...
An instruction may define part of a register where the other bits are
undefined. In that case, it is safe to rematerialize the instruction.
For example:
%vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>
The extra <imp-def> operand indicates that the instruction does not read
the other parts of the virtual register, so a remat is safe.
This patch simply allows multiple def operands for the virtual register.
It is MI->readsVirtualRegister() that determines if we depend on a
previous value so remat is impossible.
llvm-svn: 138953
2011-09-01 18:27:51 +00:00
Jim Grosbach
f6d5d60f99
ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.
...
llvm-svn: 138952
2011-09-01 18:22:13 +00:00
Bruno Cardoso Lopes
f61d1c072e
Fix vbroadcast matching logic to early unmatch if the node doesn't have
...
only one use. Fix PR10825.
llvm-svn: 138951
2011-09-01 18:15:06 +00:00
Owen Anderson
35d240f9e8
t2Bcc is allowed to have a predicate without a preceding IT instruction.
...
llvm-svn: 138946
2011-09-01 17:47:45 +00:00
Jakob Stoklund Olesen
6357fa2f06
Prevent remat of partial register redefinitions.
...
An instruction that redefines only part of a larger register can never
be rematerialized since the virtual register value depends on the old
value in other parts of the register.
This was fixed for the inline spiller in r138794. This patch fixes the
problem for all register allocators, and includes a small test case.
<rdar://problem/10032939>
llvm-svn: 138944
2011-09-01 17:18:50 +00:00
Bill Wendling
185d377597
Update to new EH scheme.
...
llvm-svn: 138933
2011-09-01 01:28:25 +00:00
Bill Wendling
d33e3007fa
Update to new EH scheme.
...
llvm-svn: 138928
2011-09-01 01:08:21 +00:00
Bill Wendling
3b17c1b48d
Update to new EH scheme.
...
llvm-svn: 138927
2011-09-01 01:02:41 +00:00
Bill Wendling
e88632d667
Update some tests to the new EH scheme.
...
llvm-svn: 138925
2011-09-01 00:58:03 +00:00
Andrew Trick
832a6a1909
PreRA scheduler should avoid cloning compares.
...
Added canClobberReachingPhysRegUse() to handle a particular pattern in
which a two-address instruction could be forced to interfere with
EFLAGS, causing a compare to be unnecessarilly cloned.
Fixes rdar://problem/5875261
llvm-svn: 138924
2011-09-01 00:54:31 +00:00
Jim Grosbach
1d3c137839
Thumb2 assembly parsing and encoding for ADD(immediate).
...
llvm-svn: 138922
2011-09-01 00:28:52 +00:00
Bill Wendling
080f40a49d
Reenable test.
...
llvm-svn: 138916
2011-08-31 23:08:05 +00:00
Bill Wendling
54b91028f0
Revert accidental commit
...
llvm-svn: 138915
2011-08-31 23:07:46 +00:00
Eli Friedman
c472975fd9
Disable this test until Bill fixes it properly.
...
llvm-svn: 138914
2011-08-31 23:03:30 +00:00
Bill Wendling
5624fe0cff
Update to new EH scheme.
...
llvm-svn: 138908
2011-08-31 21:50:07 +00:00
Bill Wendling
e336599f6d
Update to new EH scheme.
...
llvm-svn: 138906
2011-08-31 21:44:24 +00:00
Bill Wendling
55fb73a6e0
Remove old declare statements.
...
llvm-svn: 138905
2011-08-31 21:41:20 +00:00
Bill Wendling
22055c713f
Update more tests to the new EH scheme.
...
llvm-svn: 138904
2011-08-31 21:40:15 +00:00
Bill Wendling
d4e871404d
Update more tests to the new EH scheme.
...
llvm-svn: 138903
2011-08-31 21:39:05 +00:00
Eli Friedman
293c31b81c
Add tests for the transformations SCCP can do on atomic loads and stores (which are safe without any modifications).
...
llvm-svn: 138902
2011-08-31 21:37:06 +00:00
Bill Wendling
c4c24f03e9
Revert r138894. This was failing on cmake-clang-i686-msvc10.
...
llvm-svn: 138900
2011-08-31 21:20:25 +00:00
Bill Wendling
e6174a2c85
Update more tests to the new EH scheme.
...
llvm-svn: 138894
2011-08-31 21:04:11 +00:00
Bill Wendling
b1e680fd3f
Update the tests to the new EH scheme.
...
llvm-svn: 138891
2011-08-31 20:55:40 +00:00
Owen Anderson
a455a0b1e7
Fix encoding for tBcc with immediate offset operand.
...
llvm-svn: 138889
2011-08-31 20:26:14 +00:00
Jim Grosbach
6a69d6902f
Run the Thumb1 parser tests in Thumb2 mode, as well.
...
Thumb2 is a superset of Thumb1, so all of the encodings should still work.
llvm-svn: 138883
2011-08-31 19:50:28 +00:00
Jim Grosbach
6eb213c919
Thumb NOP encoding varies depending on ARCH revision.
...
llvm-svn: 138876
2011-08-31 18:35:46 +00:00
Owen Anderson
5c160fd243
Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels.
...
llvm-svn: 138874
2011-08-31 18:30:20 +00:00
Eli Friedman
7c3bdede25
Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; implements 64-bit atomic load/store for ARM.
...
llvm-svn: 138872
2011-08-31 18:26:09 +00:00
Jim Grosbach
af8c3cc710
Thumb2 parsing and encoding for ADC(register).
...
Also add instruction aliases for non-.w versions of SBC since they're the
same.
llvm-svn: 138871
2011-08-31 18:23:08 +00:00
Eli Friedman
1ccecbb9d3
64-bit atomic cmpxchg for ARM.
...
llvm-svn: 138868
2011-08-31 17:52:22 +00:00
David Greene
cdef71f4f3
Compress Repeated Byte Output
...
Emit a repeated sequence of bytes using .zero. This saves an enormous
amount of asm file space for certain programs.
llvm-svn: 138864
2011-08-31 17:30:56 +00:00
Jim Grosbach
6d606fbe14
Tweak Thumb1 ADD encoding selection a bit.
...
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.
llvm-svn: 138862
2011-08-31 17:07:33 +00:00
Benjamin Kramer
5247ca0ae5
This test requires sse, otherwise x87 ops will block tailcall optimization
...
llvm-svn: 138859
2011-08-31 16:49:05 +00:00
Bruno Cardoso Lopes
9fc6b8be03
- Move all MOVSS and MOVSD patterns close to their definitions
...
- Duplicate some store patterns to their AVX forms!
- Catched a bug while restricting the patterns subtarget, fix it
and update a testcase to check it properly
llvm-svn: 138851
2011-08-31 03:04:20 +00:00
Evan Cheng
cb1e5bae4c
Fix (movhps load) lowering / pattern to match more cases. rdar://10050549
...
llvm-svn: 138848
2011-08-31 02:05:24 +00:00
Eli Friedman
2c7bb52f56
Some minor cleanups for r138845.
...
llvm-svn: 138846
2011-08-31 00:41:05 +00:00
Eli Friedman
c3f9c4a852
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.
...
llvm-svn: 138845
2011-08-31 00:31:29 +00:00
Benjamin Kramer
50cabb5de4
Fix test typo.
...
llvm-svn: 138843
2011-08-31 00:02:59 +00:00
Rafael Espindola
a45c20b049
Remove the old tail duplication pass. It is not used and is unable to update
...
ssa, so it has to be run really early in the pipeline. Any replacement
should probably use the SSAUpdater.
llvm-svn: 138841
2011-08-30 23:03:45 +00:00
Owen Anderson
2fa06a7226
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
...
llvm-svn: 138840
2011-08-30 22:58:27 +00:00
Owen Anderson
fdf3cd7f2b
Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels.
...
llvm-svn: 138837
2011-08-30 22:15:17 +00:00
Owen Anderson
d16fb43b1f
Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels.
...
llvm-svn: 138835
2011-08-30 22:10:03 +00:00
Owen Anderson
543c89fb15
Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping.
...
llvm-svn: 138834
2011-08-30 22:03:20 +00:00
Rafael Espindola
1450f61e8f
Add a triple.
...
llvm-svn: 138831
2011-08-30 21:19:37 +00:00
Owen Anderson
b359367a3d
Remove empty file.
...
llvm-svn: 138830
2011-08-30 21:17:20 +00:00