e776b580c1
Make sure to handle the case where emitPredicateMatch returns false. Noticed by inspection.
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llvm-svn: 139317
2011-09-08 21:00:31 +00:00
21d293a37f
Fix warning on windows; use of comparison with bool argument.
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llvm-svn: 139286
2011-09-08 08:12:01 +00:00
43674ad44d
Fix a use of freed string contents.
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Speculatively try to fix our windows testers with a patch I found on the internet.
llvm-svn: 139279
2011-09-08 05:25:49 +00:00
61abca6daa
whitespace
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llvm-svn: 139278
2011-09-08 05:23:14 +00:00
8067df9503
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
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llvm-svn: 139250
2011-09-07 19:42:28 +00:00
a4043c4b32
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
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Patch by James Molloy.
llvm-svn: 137830
2011-08-17 17:44:15 +00:00
ecc4ffc941
Fix an oversight in the FixedLenDecoderEmitter where we weren't correctly checking the success result of custom decoder hooks on singleton decodings.
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llvm-svn: 137171
2011-08-09 23:05:23 +00:00
3022d6711d
Make the FixedLengthDecoderEmitter smart enough to autogenerate decoders for encodings like "let Inst{11-7} = foo;", where the RHS has no bitwidth specifiers.
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llvm-svn: 136660
2011-08-01 22:45:43 +00:00
faee2cf9ff
The FixedLenDecoder needs to gracefully handle failing per-instruction decoder hooks in addition to per-operand decoder hooks.
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llvm-svn: 136645
2011-08-01 20:06:49 +00:00
37ef826040
Enhance the fixed length disassembler to better handle operand decoding failures.
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llvm-svn: 136635
2011-08-01 18:44:37 +00:00
e08f5b5b37
Correctly handle scattered operands where the bits of the operand are contiguous, but out of order.
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llvm-svn: 136534
2011-07-29 23:01:18 +00:00
af8ee2cdee
Unconstify Inits
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Remove const qualifiers from Init references, per Chris' request.
llvm-svn: 136531
2011-07-29 22:43:06 +00:00
1aa0e3e118
[AVX] Constify Inits
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Make references to Inits const everywhere. This is the final step
before making them unique.
llvm-svn: 136485
2011-07-29 19:07:05 +00:00
cb32ce2642
Third time's the charm for implementing tied operand decoding properly.
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llvm-svn: 136478
2011-07-29 18:28:52 +00:00
abe75904a8
Fix a case where, when trying to track tied operands, we'd accidentally overwrite our mapping.
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llvm-svn: 136467
2011-07-29 17:32:03 +00:00
53562d0551
Enhance the fixed-length decoder emitter to support tied operands.
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llvm-svn: 136431
2011-07-28 23:56:20 +00:00
e3591657a0
Enhance the fixed-length decoder emitter to support parsing scattered fields.
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llvm-svn: 136405
2011-07-28 21:54:31 +00:00
c78e03c39a
Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM.
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llvm-svn: 135524
2011-07-19 21:06:00 +00:00
71520a867d
Revert r134921, 134917, 134908 and 134907. They're causing failures
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in multiple buildbots.
llvm-svn: 134936
2011-07-11 23:06:52 +00:00
af973b4f36
[AVX] Make Inits Foldable
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Manage Inits in a FoldingSet. This provides several benefits:
- Memory for Inits is properly managed
- Duplicate Inits are folded into Flyweights, saving memory
- It enforces const-correctness, protecting against certain classes
of bugs
The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen. This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.
llvm-svn: 134907
2011-07-11 18:25:51 +00:00
f3fd36e0f5
Don't require pseudo-instructions to carry encoding information.
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For now this is distinct from isCodeGenOnly, as code-gen-only
instructions can (and often do) still have encoding information
associated with them. Once we've migrated all of them over to true
pseudo-instructions that are lowered to real instructions prior to
the printer/emitter, we can remove isCodeGenOnly and just use isPseudo.
llvm-svn: 134539
2011-07-06 21:33:38 +00:00
a84be6c96b
Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0.
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Patch by Jim Grosbach.
llvm-svn: 133940
2011-06-27 21:06:21 +00:00
f2e8397b4b
Enhance the fixed-length disassembler to support the callbacks necessary for symbolic disassembly.
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llvm-svn: 129708
2011-04-18 18:42:26 +00:00
0ab5e2cded
Fix a ton of comment typos found by codespell. Patch by
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Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
0fabf10388
Ignore isCodeGenOnly instructions when generating diassembly tables.
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llvm-svn: 127619
2011-03-14 20:58:49 +00:00
4e81890d36
Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for fixed-length instruction encodings.
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A major part of its (eventual) goal is to support a much cleaner separation between disassembly callbacks
provided by the target and the disassembler emitter itself, i.e. not requiring hardcoding of knowledge in tblgen
like the existing disassembly emitters do.
The hope is that some day this will allow us to replace the existing non-Thumb ARM disassembler and remove
some of the hacks the old one introduced to tblgen.
llvm-svn: 125966
2011-02-18 21:51:29 +00:00
Eli Friedman