Commit Graph

4985 Commits

Author SHA1 Message Date
Andrew Trick 1191773a62 Generalize this test's CHECK statements to handle different indvars modes.
llvm-svn: 139577
2011-09-13 02:46:27 +00:00
Bruno Cardoso Lopes bf6e1e2717 Change testcase commandline to be more strict and silence buildbots
llvm-svn: 139554
2011-09-12 22:59:26 +00:00
Bruno Cardoso Lopes ff8d8a830e Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and
destination types are equal!

llvm-svn: 139553
2011-09-12 22:59:23 +00:00
Bruno Cardoso Lopes 973d2921e8 Revert the wrong part of r139528, and fix testcases.
llvm-svn: 139541
2011-09-12 21:24:07 +00:00
Bruno Cardoso Lopes be7a086f58 Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.
However with this fix it does now.

Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.

llvm-svn: 139528
2011-09-12 19:30:40 +00:00
Eli Friedman 57ca95961b Fix mistake in test runline.
llvm-svn: 139505
2011-09-12 17:32:58 +00:00
Richard Osborne 97a2a5c4dc Associate a MemOperand with LDWCP nodes introduced during ISel.
This information is required if we want LDWCP to be hoisted out of loops.

llvm-svn: 139495
2011-09-12 14:43:23 +00:00
Eli Friedman 501f541b45 Really un-XFAIL the testcase, like I said I would in r139458.
llvm-svn: 139459
2011-09-10 02:02:27 +00:00
Richard Trieu d9917bef6c Fixed an assert from:
assert("not implemented for target shuffle node");

to:

  assert(0 && "not implemented for target shuffle node");

This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.

llvm-svn: 139454
2011-09-10 01:26:21 +00:00
Akira Hatanaka 5624707684 Fix test cases.
Generate code for Mips32r1 unless a Mips32r2 feature is tested.

llvm-svn: 139433
2011-09-09 23:14:58 +00:00
Eli Friedman b7910b79f5 Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897.
llvm-svn: 139407
2011-09-09 21:04:06 +00:00
Akira Hatanaka 4444daeec5 Drop support for Mips1 and Mips2.
llvm-svn: 139405
2011-09-09 20:45:50 +00:00
Nadav Rotem de838daefd Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type
llvm-svn: 139400
2011-09-09 20:29:17 +00:00
Akira Hatanaka d22a1c6c95 Drop support for Allegrex. Allegrex implements a variant of Mips2.
llvm-svn: 139383
2011-09-09 19:00:51 +00:00
Akira Hatanaka df1df7edf1 Change default target architecture from Mips1 to Mips32r1 in preparation for
removing support for Mips1 and Mips2. 

This change and the ones that follow have been discussed with and approved by
Bruno.

llvm-svn: 139344
2011-09-09 01:13:27 +00:00
Devang Patel 9d904e1a97 Directly point debug info to the stack slot of the arugment, instead of trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges.
llvm-svn: 139330
2011-09-08 22:59:09 +00:00
Bruno Cardoso Lopes 46b9cde019 Add a AVX version of a simple i64 -> f64 bitcast. This could be
triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.

llvm-svn: 139320
2011-09-08 21:52:33 +00:00
Bruno Cardoso Lopes 51920a6191 Reapply testcase from r139309!
llvm-svn: 139318
2011-09-08 21:05:43 +00:00
Bruno Cardoso Lopes f483c081b6 Remove this crashing test, until I figure out what's going wrong here
llvm-svn: 139309
2011-09-08 18:32:36 +00:00
Bruno Cardoso Lopes fb113a0051 Add AVX versions of blend vector operations and fix some issues noticed
in Nadav's r139285 and r139287 commits.

1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions

llvm-svn: 139305
2011-09-08 18:05:08 +00:00
Bruno Cardoso Lopes ea8d803bb0 Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.
Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.

llvm-svn: 139304
2011-09-08 18:05:02 +00:00
Nadav Rotem e114ba4465 This test is already covered by llvm/trunk/test/CodeGen/X86/vsel.ll
llvm-svn: 139288
2011-09-08 08:43:23 +00:00
Nadav Rotem 354b7585de add a testcase for the previous patch
llvm-svn: 139287
2011-09-08 08:31:31 +00:00
Nadav Rotem 2550ba2a27 Add X86-SSE4 codegen support for vector-select.
llvm-svn: 139285
2011-09-08 08:11:19 +00:00
Eli Friedman 02f2f89a98 Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()).
This isn't exactly ideal, but it is good enough for the moment.

llvm-svn: 139245
2011-09-07 18:48:32 +00:00
Duncan Sands 1257042b70 Another forgotten trampoline testcase.
llvm-svn: 139230
2011-09-07 10:05:14 +00:00
Eli Friedman e978d2f644 Relax the MemOperands on atomics a bit. Fixes -verify-machineinstrs failures for atomic laod/store on ARM.
(The fix for the related failures on x86 is going to be nastier because we actually need Acquire memoperands attached to the atomic load instrs, etc.)

llvm-svn: 139221
2011-09-07 02:23:42 +00:00
Devang Patel 9de7a7db26 While sinking machine instructions, sink matching DBG_VALUEs also otherwise live debug variable pass will drop DBG_VALUEs on the floor.
llvm-svn: 139208
2011-09-07 00:07:58 +00:00
Nick Lewycky 474c455060 Disable these tests harder. They're XFAIL'd, but that means they still run, and
these tests all infinitely recurse, bringing my system down into swapping hell.

llvm-svn: 139192
2011-09-06 22:08:18 +00:00
Evan Cheng 0b758ed6ba Fix fall outs from my recent change on how carry bit is modeled during isel.
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745

llvm-svn: 139157
2011-09-06 18:52:20 +00:00
Jakob Stoklund Olesen 50ef7611aa Atomic pseudos don't use (as in read) CPSR. They clobber it.
llvm-svn: 139148
2011-09-06 17:40:35 +00:00
Duncan Sands a098436b32 Split the init.trampoline intrinsic, which currently combines GCC's
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC.  While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function.  To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function.  Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!).  Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC.  Patch mostly by Sanjoy Das.

llvm-svn: 139140
2011-09-06 13:37:06 +00:00
Dan Gohman 5423017526 Revert r129875, XFAILing this test for arm, since the fix was reverted.
llvm-svn: 139058
2011-09-03 00:14:24 +00:00
Jakob Stoklund Olesen 1f72dd40c7 Pseudo CMOV instructions don't clobber EFLAGS.
The explanation about a 0 argument being materialized as xor is no
longer valid.  Rematerialization will check if EFLAGS is live before
clobbering it.

The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.

This causes one less testb instruction to be generated in the cmov.ll
test case.

llvm-svn: 139057
2011-09-02 23:52:55 +00:00
Bill Wendling 4aa2573748 Try to eliminate the use of the 'unwind' instruction.
llvm-svn: 139046
2011-09-02 22:41:11 +00:00
Eli Friedman f3dd6da7a8 Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.
llvm-svn: 139044
2011-09-02 22:33:24 +00:00
Bill Wendling 912668d998 Better fix for this testcase. Update it to the new EH scheme entirely.
llvm-svn: 139039
2011-09-02 21:27:08 +00:00
Bill Wendling 17706bcffb Update for new EH stuff. (I'm not sure if this is 100% correct.)
llvm-svn: 139038
2011-09-02 21:24:17 +00:00
Duncan Sands 5c04c62765 Darwin wants ctors/dtors to be ordered the other way round to linux.
llvm-svn: 139015
2011-09-02 18:07:19 +00:00
Kalle Raiskila f5769c1070 Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.
llvm-svn: 139004
2011-09-02 10:05:01 +00:00
Dan Gohman 3767be9aee Revert r131152, r129796, r129761. This code is currently considered
to be unreliable on platforms which require memcpy calls, and it is
complicating broader legalize cleanups. It is hoped that these cleanups
will make memcpy byval easier to implement in the future.

llvm-svn: 138977
2011-09-01 23:07:08 +00:00
Benjamin Kramer 6397051ece Don't drop alignment info on local common symbols.
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm

Based on a patch by NAKAMURA Takumi.

Fixes PR9337, PR9483 and PR10128.

llvm-svn: 138976
2011-09-01 23:04:27 +00:00
Benjamin Kramer c032617581 XFAIL this test on arm until the backend is fixed.
llvm-svn: 138955
2011-09-01 18:40:03 +00:00
Benjamin Kramer 0f6ff8cb2b This test depends on cmov being available.
llvm-svn: 138954
2011-09-01 18:40:01 +00:00
Jakob Stoklund Olesen 5dc87d0f4d Permit remat of partial register defs when it is safe.
An instruction may define part of a register where the other bits are
undefined. In that case, it is safe to rematerialize the instruction.
For example:

  %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>

The extra <imp-def> operand indicates that the instruction does not read
the other parts of the virtual register, so a remat is safe.

This patch simply allows multiple def operands for the virtual register.
It is MI->readsVirtualRegister() that determines if we depend on a
previous value so remat is impossible.

llvm-svn: 138953
2011-09-01 18:27:51 +00:00
Bruno Cardoso Lopes f61d1c072e Fix vbroadcast matching logic to early unmatch if the node doesn't have
only one use. Fix PR10825.

llvm-svn: 138951
2011-09-01 18:15:06 +00:00
Jakob Stoklund Olesen 6357fa2f06 Prevent remat of partial register redefinitions.
An instruction that redefines only part of a larger register can never
be rematerialized since the virtual register value depends on the old
value in other parts of the register.

This was fixed for the inline spiller in r138794.  This patch fixes the
problem for all register allocators, and includes a small test case.

<rdar://problem/10032939>

llvm-svn: 138944
2011-09-01 17:18:50 +00:00
Andrew Trick 832a6a1909 PreRA scheduler should avoid cloning compares.
Added canClobberReachingPhysRegUse() to handle a particular pattern in
which a two-address instruction could be forced to interfere with
EFLAGS, causing a compare to be unnecessarilly cloned.
Fixes rdar://problem/5875261

llvm-svn: 138924
2011-09-01 00:54:31 +00:00
Bill Wendling 55fb73a6e0 Remove old declare statements.
llvm-svn: 138905
2011-08-31 21:41:20 +00:00
Bill Wendling 22055c713f Update more tests to the new EH scheme.
llvm-svn: 138904
2011-08-31 21:40:15 +00:00