8c0b4d0791
Convert more SelectionDAG functions to use ArrayRef.
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llvm-svn: 207397
2014-04-28 05:57:50 +00:00
64941d9786
Convert SelectionDAG::getMergeValues to use ArrayRef.
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llvm-svn: 207374
2014-04-27 19:20:57 +00:00
48d114bed1
Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>.
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llvm-svn: 207327
2014-04-26 18:35:24 +00:00
de1c3410c3
R600: Fix function name printing in LowerCall
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v2: Check both ExternalSymbol and GlobalAddress
Patch by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 207282
2014-04-25 22:22:01 +00:00
062a2baef0
[C++] Use 'nullptr'. Target edition.
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llvm-svn: 207197
2014-04-25 05:30:21 +00:00
16353871c3
R600: Emit error instead of unreachable on function call
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llvm-svn: 206904
2014-04-22 16:42:00 +00:00
a3c8cde77b
R600: Change how vector truncating stores are packed.
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Don't introduce new operations on an illegal sub 32-bit type.
Do the operations on a 32-bit value, and then use a truncating store.
llvm-svn: 206864
2014-04-22 04:11:14 +00:00
5dbd5db518
R600: Make sign_extend_inreg legal.
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Don't know why I didn't just do this in the first place.
llvm-svn: 206862
2014-04-22 03:49:30 +00:00
aeeea8a864
R600: Add comment clariying use of sext for result of MUL_U24
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llvm-svn: 206501
2014-04-17 21:00:13 +00:00
4e46665a80
R600: Expand sign extension of vectors.
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Setting vector types to expand will result in scalarization on pre SI hw,
as those gpus don't have vector shifts either.
Expand also i32 vectors, this helps llvm make the correct decision
about scalarizing the vector ops.
v2: move setOperation() calls to R600ISelLowering.cpp.
cleanup the SI code to make it obvious that this patch does is nop for SI
Patch by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 206348
2014-04-16 01:41:30 +00:00
470acd81a8
R600/SI: Fix loads of i1
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llvm-svn: 206330
2014-04-15 22:28:39 +00:00
aad475b324
Break PseudoSourceValue out of the Value hierarchy. It is now the root of its own tree containing FixedStackPseudoSourceValue (which you can use isa/dyn_cast on) and MipsCallEntry (which you can't). Anything that needs to use either a PseudoSourceValue* and Value* is strongly encouraged to use a MachinePointerInfo instead.
...
llvm-svn: 206255
2014-04-15 07:22:52 +00:00
9ec3cf2c8a
Move ExtractVectorElements to SelectionDAG.
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This seems generally useful, and makes sense to
go along with SplitVector.
llvm-svn: 206041
2014-04-11 17:47:30 +00:00
50122a5890
R600: Match 24-bit arithmetic patterns in a Target DAGCombine
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Moving these patterns from TableGen files to PerformDAGCombine()
should allow us to generate better code by eliminating unnecessary
shifts and extensions earlier.
This also fixes a bug where the MAD pattern was calling
SimplifyDemandedBits with a 24-bit mask on the first operand
even when the full pattern wasn't being matched. This occasionally
resulted in some instructions being incorrectly deleted from the
program.
v2:
- Fix bug with 64-bit mul
llvm-svn: 205731
2014-04-07 19:45:41 +00:00
7939acd7fa
Use .data() instead of &x[0]
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llvm-svn: 205722
2014-04-07 16:44:24 +00:00
378bf9c68b
R600: Compute masked bits for min and max
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llvm-svn: 205242
2014-03-31 19:35:33 +00:00
4c53717787
R600: Add BFE, BFI, and BFM intrinsics to help with writing tests.
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llvm-svn: 205236
2014-03-31 18:21:18 +00:00
b34583661b
R600: Add target nodes for BFM and BFI
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llvm-svn: 205235
2014-03-31 18:21:13 +00:00
b517c8128e
R600: Implement isZExtFree.
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This allows 64-bit operations that are truncated to be reduced
to 32-bit ones.
llvm-svn: 204946
2014-03-27 17:23:31 +00:00
d125d74a73
R600/SI: Fix unreachable with a sext_in_reg to an illegal type.
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llvm-svn: 204945
2014-03-27 17:23:24 +00:00
90b733a3cf
R600: Add a testcase for sext_in_reg I missed.
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This sext_inreg i32 in i64 case was already handled, but not enabled.
llvm-svn: 204840
2014-03-26 18:31:06 +00:00
0c274feedf
R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp
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Remove handling of select_cc, since it makes no sense to be there. This
now does nothing, but I'll be adding some handling of other target nodes
soon.
llvm-svn: 204743
2014-03-25 18:18:27 +00:00
a7f1e0c44f
R600: Implement isNarrowingProfitable.
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llvm-svn: 204658
2014-03-24 19:43:31 +00:00
fae02989b7
R600: Match sign_extend_inreg to BFE instructions
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llvm-svn: 204072
2014-03-17 18:58:11 +00:00
ea330fbe49
R600: Remove unnecessary attempt to zext a pointer.
...
Private pointers are now always 32-bits.
llvm-svn: 203989
2014-03-15 00:08:26 +00:00
74891cdefe
R600: Code cleanup.
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Use sign_extend_inreg and getZeroExtendInReg instead of
using the bit operations they expand into.
llvm-svn: 203988
2014-03-15 00:08:22 +00:00
e389dd5d68
R600: Fix trunc store from i64 to i1
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llvm-svn: 203695
2014-03-12 18:45:52 +00:00
0211714ecb
R600: Calculate store mask instead of using switch.
...
llvm-svn: 203527
2014-03-11 01:38:53 +00:00
9504d2f269
Use .data() instead of &x[0]
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llvm-svn: 203516
2014-03-11 00:01:31 +00:00
f9a995d68c
R600: Fix extloads from i8 / i16 to i64.
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This appears to only be working for global loads. Private
and local break for other reasons.
llvm-svn: 203135
2014-03-06 17:34:12 +00:00
9fe669c522
R600/SI: Expand selects on vectors.
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llvm-svn: 203134
2014-03-06 17:34:03 +00:00
ca6dcfcf59
Fix typo
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llvm-svn: 203013
2014-03-05 21:47:22 +00:00
41e2f2bacd
R600/SI - Add new CI arithmetic instructions.
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Does not yet include larger part required
to match v_mad_i64_i32 / v_mad_u64_u32.
llvm-svn: 202077
2014-02-24 21:01:28 +00:00
21a3faaf25
Fix DOT4 missing from getTargetOpcodeName
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llvm-svn: 202075
2014-02-24 21:01:21 +00:00
967bf5813f
R600/SI: Expand all v8[if]32 operations
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llvm-svn: 201371
2014-02-13 23:34:15 +00:00
53f9df4c93
R600: Always implement both versions of isTruncateFree and add a sanity check.
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llvm-svn: 201222
2014-02-12 10:17:54 +00:00
0cdcd961bf
R600: Implement isTruncateFree
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Truncation is just accessing a subregister for any multiple of
the register size, so it's free.
llvm-svn: 201107
2014-02-10 19:57:42 +00:00
aeb456438c
R600/SI: Expand i1 BR_CC
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This fixes a crashes in the OpenCV test suite and also the scrypt
kernel in bfgminer.
I was unable to come up with a reduced test case for this.
https://bugs.freedesktop.org/show_bug.cgi?id=72785
llvm-svn: 200776
2014-02-04 17:18:43 +00:00
bfebd1fc7e
R600: Enable vector fpow.
...
The OpenCL specs say: "The vector versions of the math functions operate
component-wise. The description is per-component."
Patch by: Jan Vesely
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 200773
2014-02-04 17:18:37 +00:00
04c0e9851b
R600: Add support for global addresses with constant initializers
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llvm-svn: 199825
2014-01-22 19:24:21 +00:00
e93736057f
R600/SI: Add support for i8 and i16 private loads/stores
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llvm-svn: 199823
2014-01-22 19:24:14 +00:00
eddfa69465
R600: Allow ftrunc
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v2: Add ftrunc->TRUNC pattern instead of replacing int_AMDGPU_trunc
v3: move ftrunc pattern next to TRUNC definition, it's available since R600
Patch By: Jan Vesely
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 197783
2013-12-20 05:11:55 +00:00
52226f9a8e
Don't manually calculate size in bytes
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llvm-svn: 197327
2013-12-14 18:21:59 +00:00
eaa3a7efab
Use llvm_unreachable instead of assert(0)
...
llvm-svn: 196971
2013-12-10 21:37:42 +00:00
175e7a8c97
R600: Expand vector FABS
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NOTE: This is a candidate for the 3.4 branch.
llvm-svn: 195881
2013-11-27 21:23:39 +00:00
4d566b2edf
R600: Add support for ISD::FROUND
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NOTE: This is a candidate for the 3.4 branch.
llvm-svn: 195878
2013-11-27 21:23:20 +00:00
c5559bb14b
Add target hook to prevent folding some bitcasted loads.
...
This is to avoid this transformation in some cases:
fold (conv (load x)) -> (load (conv*)x)
On architectures that don't natively support some vector
loads efficiently casting the load to a smaller vector of
larger types and loading is more efficient.
Patch by Micah Villmow.
llvm-svn: 194783
2013-11-15 04:42:23 +00:00
81d871dee3
R600/SI: Add support for private address space load/store
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Private address space is emulated using the register file with
MOVRELS and MOVRELD instructions.
llvm-svn: 194626
2013-11-13 23:36:50 +00:00
4f3751f2af
R600: Fix LowerUDIVREM
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llvm-svn: 194153
2013-11-06 17:36:04 +00:00
c947d8ca64
R600: Custom lower f32 = uint_to_fp i64
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llvm-svn: 193701
2013-10-30 17:22:05 +00:00
Craig Topper