1e9e49f421
fix this to not be completely broken.
...
llvm-svn: 115164
2010-09-30 17:04:59 +00:00
c8f0e29b5e
update, unxfail, fix bogus encodings.
...
llvm-svn: 115163
2010-09-30 17:03:20 +00:00
a9e913e139
update and unxfail
...
llvm-svn: 115162
2010-09-30 17:00:53 +00:00
ccf2c765f0
unxfail this by fixing syntactic differences.
...
llvm-svn: 115161
2010-09-30 16:59:28 +00:00
4373badcdf
implement support for finit, PR8258
...
llvm-svn: 115156
2010-09-30 16:42:53 +00:00
adc0dbe470
add support for fstcw, PR8259
...
llvm-svn: 115154
2010-09-30 16:39:29 +00:00
2b43c1cf42
implement rdar://8491845 - Gas supports commuted forms of non-commutable instructions.
...
llvm-svn: 115061
2010-09-29 18:39:16 +00:00
8f7851d2b4
fix rdar://8490728 - llvm-mc rejects gpr64 form of 'movmskpd'
...
llvm-svn: 115029
2010-09-29 05:05:03 +00:00
52e6020883
add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382
...
llvm-svn: 115027
2010-09-29 04:55:40 +00:00
5da7f9fcfd
make the x86 mccode emitter emit the 0x67 and 0x66 prefix bytes in the same
...
order as cctools for diffability.
llvm-svn: 115022
2010-09-29 03:43:43 +00:00
a4e1c74947
implement support for 32-bit address operands in 64-bit mode, which
...
are defined to emit the 0x67 prefix byte. rdar://8482675
llvm-svn: 115021
2010-09-29 03:33:25 +00:00
f60062fd55
add basic avx support to the disassembler, also teach it about ssmem/sdmem
...
operands.
With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up. This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'
llvm-svn: 115019
2010-09-29 02:57:56 +00:00
ff3a3930a0
add asmparser support for cvttpd2dq by removing some Int_ prefixes.
...
Clean up cvttps2dq by removing some redundant implementations of the
same instruction. rdar://8456382
llvm-svn: 115018
2010-09-29 02:36:32 +00:00
ef1c2fc305
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes.
...
llvm-svn: 115017
2010-09-29 02:24:57 +00:00
a63292a3ca
implement rdar://8456378 and PR7557 - support for the fstsw,
...
an instruction that requires a WHOLE NEW wonderful kind of alias.
llvm-svn: 115015
2010-09-29 01:50:45 +00:00
d116d8a4e9
MC/AsmParser: Handle exponents in floating point literals.
...
llvm-svn: 114861
2010-09-27 20:12:52 +00:00
b6a7f97c88
yet more aliases.
...
llvm-svn: 114822
2010-09-27 07:24:57 +00:00
882626cd5b
add a couple more aliases, rdar://8456378
...
llvm-svn: 114821
2010-09-27 07:21:41 +00:00
972c60d821
fix rdar://8470918 - llvm-mc can't assemble smovl
...
llvm-svn: 114819
2010-09-27 07:11:53 +00:00
ff0062af62
Fix rdar://8468087 - llvm-mc commutes fmul (and friend) operands.
...
My previous fix for rdar://8456371 should only apply to fmulp/faddp,
not to fmul/fadd. Instruction set orthogonality is overrated or
something.
llvm-svn: 114818
2010-09-27 07:08:21 +00:00
4f59cbfb66
implement support for 'clr' alias. This is part of rdar://8416805,
...
but balrog was wanting it on irc.
llvm-svn: 114809
2010-09-27 04:23:03 +00:00
ce17f72c38
MC/AsmParser: Handle a missed case of floating literals in the lexer.
...
llvm-svn: 114733
2010-09-24 17:10:26 +00:00
2af1653032
MC/AsmParser: Support .single and .double for embedding floating point literals.
...
- I believe more modern 'gas' supports a more enhanced set of arithmetic on
them, but for now the only thing we can do is emit them as data.
llvm-svn: 114719
2010-09-24 01:59:56 +00:00
415624cf3f
fix rdar://8456371 - Handle commutable instructions written backward.
...
llvm-svn: 114536
2010-09-22 06:26:39 +00:00
bd85725341
Fix an inconsistency in the x86 backend that led it to reject "calll foo" on
...
x86-32: 32-bit calls were named "call" not "calll". 64-bit calls were correctly
named "callq", so this only impacted x86-32.
This fixes rdar://8456370 - llvm-mc rejects 'calll'
This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
I will file a bugzilla.
llvm-svn: 114534
2010-09-22 05:49:14 +00:00
37fc469f88
fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8"
...
Teaching the code generator about CR8-15, how to rex them up, etc.
llvm-svn: 114533
2010-09-22 05:29:50 +00:00
2bb9504d1a
fix rdar://8456417 - llvm-mc can't do basic math
...
llvm-svn: 114532
2010-09-22 05:05:16 +00:00
9dfd2e354e
add the missing aliases for fp stack cmovs, rdar://8456391
...
llvm-svn: 114531
2010-09-22 04:56:20 +00:00
1261b81e82
Fix rdar://8456364 - llvm-mc rejects '%CS'
...
llvm-svn: 114528
2010-09-22 04:11:10 +00:00
39cf8deded
fix rdar://8456389 - llvm-mc mismatch with 'as' on 'fstp'
...
-This line, and those below, will be ignored--
M test/MC/AsmParser/X86/x86_instructions.s
M lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm-svn: 114527
2010-09-22 04:04:03 +00:00
a91e510f94
fix rdar://8456361 - llvm-mc rejects 'rep movsd'
...
llvm-svn: 114526
2010-09-22 03:50:32 +00:00
cea0a8d7ae
fix rdar://8444631 - encoder crash on 'enter'
...
What a weird instruction.
llvm-svn: 114190
2010-09-17 18:02:29 +00:00
55f16678e4
MC/AsmParser: Add support for 'a + 4@GOTPCREL' and friends, by reconsing the
...
expression to include the modifier.
- Gross, but this a corner case we don't expect to see often in practice, but
it is worth accepting.
- Also improves diagnostics on invalid modifiers.
llvm-svn: 114154
2010-09-17 02:47:07 +00:00
74d320db97
fix rdar://8438816 - unrecognized 'fildq' instruction
...
llvm-svn: 114116
2010-09-16 20:46:38 +00:00
ee7e6f42f8
lcall and ljmp always default to lcalll and ljmpl. This finally
...
wraps up r8418316
llvm-svn: 113949
2010-09-15 05:30:20 +00:00
09bfe645f6
apparently jmpl $1,$2 is an alias for ljmpl, similiarly
...
for call. Add this.
llvm-svn: 113948
2010-09-15 05:25:21 +00:00
6757eae45e
Disambiguate lcall/ljmp to the 32-bit version. This happens
...
even in 64-bit mode apparently.
llvm-svn: 113945
2010-09-15 05:14:54 +00:00
5be87c619b
fix the encoding of sldt GR16 to have the 0x66 prefix, and
...
add sldt GR32, which isn't documented in the intel manual
but which gas accepts. Part of rdar://8418316
llvm-svn: 113938
2010-09-15 04:45:10 +00:00
6b40b0def1
implement aliases for shld/shrd, part of rdar://8418316
...
llvm-svn: 113937
2010-09-15 04:37:18 +00:00
4bd21710b6
fix rdar://8431880 - rcl/rcr with no shift amount not recognized
...
llvm-svn: 113936
2010-09-15 04:33:27 +00:00
81ce173860
add various broken forms of fnstsw. I didn't add the %rax
...
version because it adds a prefix and makes even less sense
than the other broken forms. This wraps up rdar://8431422
llvm-svn: 113932
2010-09-15 04:15:16 +00:00
7df35dbd19
add some aliases for f[u]comi, part of rdar://8431422
...
llvm-svn: 113930
2010-09-15 04:08:38 +00:00
4dbcba0082
add a bunch of aliases for fp operations with no operand,
...
rdar://8431422
llvm-svn: 113929
2010-09-15 04:04:33 +00:00
5f2311dc29
add a terrible hack to allow out with dx is parens, a gas bug.
...
This fixes PR8114
llvm-svn: 113894
2010-09-14 23:34:29 +00:00
1bbb14ab8f
add a missed cmov alias, part of rdar://8416805
...
llvm-svn: 113693
2010-09-11 17:08:22 +00:00
3340c3e86c
add support for all the setCC aliases. Part of rdar://8416805
...
llvm-svn: 113692
2010-09-11 17:06:05 +00:00
b47c042e09
add support for pushfd/popfd which are aliases for pushfl/popfl.
...
This fixes rdar://8408129 - pushfd and popfd get invalid instruction mnemonic errors
llvm-svn: 113690
2010-09-11 16:39:16 +00:00
30561aba20
implement rdar://8407928 - support for in/out with a missing "a" register.
...
llvm-svn: 113689
2010-09-11 16:32:12 +00:00
e5444a88cd
llvm-mc: Don't crash when using -n and we see a directive before the initial section.
...
- This is annoying, because we have to scatter this check everywhere that could emit real data, but I see no better solution.
llvm-svn: 113552
2010-09-09 22:42:59 +00:00
43325c4a68
llvm-mc: Make sure we exit != 0 if any errors are encountered.
...
llvm-svn: 113551
2010-09-09 22:42:56 +00:00
28a9c2f89a
fix rdar://8407548, I missed the commuted form of xchg/test without a suffix.
...
llvm-svn: 113427
2010-09-08 22:27:05 +00:00
8ead237758
fix bugs in push/pop segment support, rdar://8407242
...
llvm-svn: 113422
2010-09-08 22:13:08 +00:00
2907d2e419
add support for the commuted form of the test instruction, rdar://8018260.
...
llvm-svn: 113352
2010-09-08 05:51:12 +00:00
a9ca7837e4
implement proper support for sysret{,l,q}, rdar://8403907
...
llvm-svn: 113350
2010-09-08 05:45:34 +00:00
063363fa80
implement the iret suite of instructions properly,
...
fixing rdar://8403974
llvm-svn: 113349
2010-09-08 05:38:31 +00:00
086a83afb1
add support for instruction prefixes on the same line as the instruction,
...
implementing rdar://8033482 and PR7254.
llvm-svn: 113348
2010-09-08 05:17:37 +00:00
8caea68a4f
gas accepts xchg <mem>, <reg> as a synonym for xchg <reg>, <mem>.
...
Add this to the mc assembler, fixing PR8061
llvm-svn: 113346
2010-09-08 04:53:27 +00:00
4703cb4a96
fix the encoding of the "jump on *cx" family of instructions,
...
rdar://8061602
llvm-svn: 113343
2010-09-08 04:30:51 +00:00
30bb384944
add missing cmov aliases, this resolves rdar://8208499
...
llvm-svn: 113189
2010-09-07 00:05:45 +00:00
7ece716da2
"sldt <mem>" is ambiguous in 64-bit mode, but should
...
always be disambiguated as sldtw. sldtw and sldtq with
a mem operands have the same effect, but sldtw is more
compact. Force it to sldtw, resolving rdar://8017530
llvm-svn: 113186
2010-09-06 23:51:44 +00:00
415e04fad2
fix rdar://8017621 - llvm-mc can't guess encoding for "push $(1000)"
...
llvm-svn: 113184
2010-09-06 23:40:56 +00:00
34e366b45c
fix the operand constraints of the immediate form of in/out,
...
allowing unsigned 8-bit operands. This fixes rdar://8208481
llvm-svn: 113182
2010-09-06 23:29:05 +00:00
e39017cb97
Add AsmParser support for the ELF .previous directive. Patch by Roman Divacky.
...
llvm-svn: 112849
2010-09-02 18:53:37 +00:00
112b6ee3f2
fixme accomplished
...
llvm-svn: 112386
2010-08-28 20:40:28 +00:00
3d148ac089
X86: Fix misencode of RI64mi8. This fixes OpenSSL / x86_64-apple-darwin10 / clang -O3.
...
llvm-svn: 112089
2010-08-25 21:11:02 +00:00
1c8d777c93
MC/X86: Tweak imul recognition, previous hack only applies for the imul form
...
taking immediates.
llvm-svn: 111950
2010-08-24 19:37:56 +00:00
09392785b4
MC/X86: Add custom hack for recognizing "imul $12, %eax" and friends.
...
llvm-svn: 111947
2010-08-24 19:24:18 +00:00
2476432639
MC/AsmParser: Change ParseExpression to use ParseIdentifier(), to support
...
dollars in identifiers.
llvm-svn: 111946
2010-08-24 19:13:42 +00:00
94b84a19b9
MC/X86: Warn on scale factors > 1 without index register, instead of erroring,
...
for 'as' compatibility.
llvm-svn: 111945
2010-08-24 19:13:38 +00:00
3b96ffdac1
MC/Parser: Accept leading dollar signs in identifiers.
...
- Implemented by manually splicing the tokens. If this turns out to be
problematically platform specific, a more elegant solution would be to
implement some context dependent lexing support.
llvm-svn: 111934
2010-08-24 18:12:12 +00:00
02db8f6415
fix rdar://7997827 - Accept and ignore LL and ULL suffixes on integer literals.
...
Also fix 0b010 syntax to actually work while we're at it :-)
llvm-svn: 111876
2010-08-24 00:43:25 +00:00
f547740d3f
fix PR7465, mishandling of lcall and ljmp: intersegment long
...
call and jumps.
llvm-svn: 111496
2010-08-19 01:18:43 +00:00
7d7b4d1b0f
MC/X86/AsmParser: Give an explicit error message when we reject an instruction
...
because it could have an ambiguous suffix.
llvm-svn: 110890
2010-08-12 00:55:42 +00:00
188b47b214
MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form.
...
llvm-svn: 110794
2010-08-11 06:37:20 +00:00
d215976208
MC/AsmParser: Fix a bug in macro argument parsing, which was dropping
...
parentheses from argument lists.
llvm-svn: 110692
2010-08-10 17:38:52 +00:00
57e3f71538
tests: Mark MC/AsmParser tests as requiring x86 for now -- almost all of them
...
rely on using a specific x86 triple to test what they want to test.
llvm-svn: 110337
2010-08-05 15:44:15 +00:00
306a1f9721
Support x86 "eiz" and "riz" pseudo index registers in the assembler.
...
llvm-svn: 109295
2010-07-24 00:06:39 +00:00
fbd7f65248
Consolidate the ELF section directive tests into a single file as
...
suggested by Chris Lattner.
llvm-svn: 109290
2010-07-23 23:40:41 +00:00
6f38011196
Move AVX encoding tests to different files
...
llvm-svn: 109269
2010-07-23 21:25:26 +00:00
ea0e05a3ce
Add AVX version of CLMUL instructions
...
llvm-svn: 109248
2010-07-23 18:41:12 +00:00
acd9230b1b
Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual
...
llvm-svn: 109204
2010-07-23 00:54:35 +00:00
0710c74f29
Add remaining AVX instructions (most of them dealing with GR64 destinations. This complete the assembler support for the general AVX ISA. But we still miss instructions from FMA3 and CLMUL specific feature flags, which are now the next step
...
llvm-svn: 109168
2010-07-22 21:18:49 +00:00
e3acfd4d58
Add more 256-bit forms for a bunch of regular AVX instructions
...
Add 64-bit (GR64) versions of some instructions (which are not
described in their SSE forms, but are described in AVX)
llvm-svn: 109063
2010-07-21 23:53:50 +00:00
6238c1d102
Add missing AVX convert instructions. Those instructions are not described in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it
...
llvm-svn: 109039
2010-07-21 21:37:59 +00:00
cdbec62510
Add AVX only vzeroall and vzeroupper instructions
...
llvm-svn: 109002
2010-07-21 08:56:24 +00:00
3499934da6
Add new AVX vpermilps, vpermilpd and vperm2f128 instructions
...
llvm-svn: 108984
2010-07-21 03:07:42 +00:00
3ceaf7a0a2
Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it
...
llvm-svn: 108983
2010-07-21 02:46:58 +00:00
e706501975
Add new AVX vextractf128 instructions
...
llvm-svn: 108964
2010-07-20 23:19:02 +00:00
c3eb5e3d4b
Include some tests for the recently committed ELF section directive
...
handlers.
llvm-svn: 108938
2010-07-20 21:37:30 +00:00
3b505848fd
Add new AVX instruction vinsertf128
...
llvm-svn: 108892
2010-07-20 19:44:51 +00:00
6c8041ea34
x86_32 tests for vbroadcast
...
llvm-svn: 108789
2010-07-20 00:11:50 +00:00
14c5fd437c
Add AVX vbroadcast new instruction
...
llvm-svn: 108788
2010-07-20 00:11:13 +00:00
9de0ca73d4
Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!
...
llvm-svn: 108769
2010-07-19 23:32:44 +00:00
9db7d0addd
X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same
...
instruction, we only want to allow the one for the current subtarget.
- This also fixes suffix matching for jmp instructions, because it eliminates
the ambiguity between 'jmpl' and 'jmpq'.
llvm-svn: 108746
2010-07-19 20:44:16 +00:00
9aefb8ee4c
X86-64: Mark WINCALL and more tail call instructions as code gen only.
...
llvm-svn: 108685
2010-07-19 07:21:07 +00:00
b82cd9319b
MC/X86: We now match instructions like "incl %eax" correctly for the arch we are
...
assembling; remove crufty custom cleanup code.
llvm-svn: 108681
2010-07-19 06:14:54 +00:00
af75e1923c
tests: Force another triple.
...
llvm-svn: 108666
2010-07-19 00:43:58 +00:00
3b4621103a
tests: Force triples.
...
llvm-svn: 108658
2010-07-18 21:16:10 +00:00
40a564f09f
MC/AsmParser: Fix .abort and .secure_log_unique to accept arbitrary token
...
sequences, not just strings.
llvm-svn: 108655
2010-07-18 20:15:59 +00:00
6fb1c3ad8a
MC/AsmParser: Add macro argument substitution support.
...
llvm-svn: 108654
2010-07-18 19:00:10 +00:00
4323571efb
MC/AsmParser: Add basic support for macro instantiation.
...
llvm-svn: 108653
2010-07-18 18:54:11 +00:00
c1f58ec83c
MC/AsmParser: Add basic parsing support for .macro definitions.
...
llvm-svn: 108652
2010-07-18 18:47:21 +00:00
828984ff4e
MC/AsmParser: Add .macros_{off,on} support, not that makes sense since we don't
...
support macros.
llvm-svn: 108649
2010-07-18 18:38:02 +00:00
ceb16a5ce9
Test for ELF .size directive.
...
llvm-svn: 108607
2010-07-17 03:15:24 +00:00
6c6c14a55c
Add AVX 256-bit compare instructions and a bunch of testcases
...
llvm-svn: 108286
2010-07-13 22:06:38 +00:00
fd8bfcd6e1
AVX 256-bit conversion instructions
...
Add the x86 VEX_L form to handle special cases where VEX_L must be set.
llvm-svn: 108274
2010-07-13 21:07:28 +00:00
dff283e146
Add AVX 256-bit packed logical forms
...
llvm-svn: 108224
2010-07-13 02:38:35 +00:00
36b32aeaa5
Add AVX 256-bit unop arithmetic instructions
...
llvm-svn: 108223
2010-07-13 01:53:31 +00:00
8e67a0482e
Add AVX 256 binary arithmetic instructions
...
llvm-svn: 108207
2010-07-12 23:04:15 +00:00
f9bcaad76d
Add AVX 256-bit MOVMSK forms
...
llvm-svn: 108184
2010-07-12 20:06:32 +00:00
d388c93f87
MC/AsmParser: Move .tbss and .zerofill parsing to Darwin specific parser.
...
llvm-svn: 108180
2010-07-12 19:37:35 +00:00
63a379dd5c
MC/AsmParser: Move .desc parsing to Darwin specific parser.
...
llvm-svn: 108179
2010-07-12 19:22:53 +00:00
ae9da1481a
MC/AsmParser: Move some misc. Darwin directive handling to DarwinAsmParser.
...
llvm-svn: 108174
2010-07-12 18:49:22 +00:00
2419606bfb
Add AVX 256-bit packed MOVNT variants
...
llvm-svn: 108021
2010-07-09 21:42:42 +00:00
6bc772eec7
Add AVX 256-bit unpack and interleave
...
llvm-svn: 108017
2010-07-09 21:20:35 +00:00
792e906bef
Start the support for AVX instructions with 256-bit %ymm registers. A couple of
...
notes:
- The instructions are being added with dummy placeholder patterns using some 256
specifiers, this is not meant to work now, but since there are some multiclasses
generic enough to accept them, when we go for codegen, the stuff will be already
there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
file.
llvm-svn: 107996
2010-07-09 18:27:43 +00:00
9f034c1e5d
Rework segment prefix emission code to handle segments
...
in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax
This fixes rdar://8127102. I have several cleanup patches coming
next.
llvm-svn: 107917
2010-07-08 22:28:12 +00:00
ac5881295c
Implement the major chunk of PR7195: support for 'callw'
...
in the integrated assembler. Still some discussion to be
done.
llvm-svn: 107825
2010-07-07 22:27:31 +00:00
6c61451011
Add more assembly opcodes for SSE compare instructions
...
llvm-svn: 107823
2010-07-07 22:24:03 +00:00
fd8060335b
Add AVX AES instructions
...
llvm-svn: 107798
2010-07-07 18:24:20 +00:00
6d122aef97
Add AVX SSE4.2 instructions
...
llvm-svn: 107752
2010-07-07 03:39:29 +00:00
8f5472a8e8
Add AVX SSE4.1 insertps, ptest and movntdqa instructions
...
llvm-svn: 107747
2010-07-07 01:14:56 +00:00
6430c7350d
Add AVX SSE4.1 extractps and pinsr instructions
...
llvm-svn: 107746
2010-07-07 01:01:13 +00:00
f3116ebe96
Add AVX SSE4.1 Extract Integer instructions
...
llvm-svn: 107740
2010-07-07 00:07:24 +00:00
1f9ad516c6
Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions
...
llvm-svn: 107723
2010-07-06 23:15:17 +00:00
35702d27c4
Add part of AVX SSE4.1 packed move with sign/zero extend instructions
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llvm-svn: 107720
2010-07-06 23:01:41 +00:00
e2bd058d32
Add AVX vblendvpd, vblendvps and vpblendvb instructions
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Update VEX encoding to support those new instructions
llvm-svn: 107715
2010-07-06 22:36:24 +00:00
ca99012ac0
Add AVX SSE4.1 blend, mpsadbw and vdp
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llvm-svn: 107560
2010-07-03 01:37:03 +00:00
bc75502f09
Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions
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llvm-svn: 107558
2010-07-03 01:15:47 +00:00
fc9cdc4d61
Add AVX SSE4.1 Horizontal Minimum and Position instruction
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llvm-svn: 107552
2010-07-03 00:49:21 +00:00
621c85b038
Add AVX SSE4.1 round instructions
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llvm-svn: 107549
2010-07-03 00:37:44 +00:00
c7111fd355
- Add support for the rest of AVX SSE3 instructions
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- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode
llvm-svn: 107523
2010-07-02 22:06:54 +00:00
5e88700f28
Move SSE3 Move patterns to a more appropriate section
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Add AVX SSE3 packed horizontal and & sub instructions
llvm-svn: 107405
2010-07-01 17:35:02 +00:00
886ee33a38
Add AVX SSE3 packed addsub instructions
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llvm-svn: 107404
2010-07-01 17:08:18 +00:00
a7a0c83563
Add AVX SSE3 replicate and convert instructions
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llvm-svn: 107375
2010-07-01 02:33:39 +00:00
05166740eb
- Add AVX SSE2 Move doubleword and quadword instructions.
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- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
in the .td file now have a AVX encoded form already working.
llvm-svn: 107365
2010-07-01 01:20:06 +00:00
cbcebe2950
Add AVX SSE2 mask creation and conditional store instructions
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llvm-svn: 107306
2010-06-30 18:38:10 +00:00
d079c91683
Add AVX SSE2 packed integer extract/insert instructions
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llvm-svn: 107293
2010-06-30 17:03:03 +00:00
e82689fea2
Add AVX SSE2 integer unpack instructions
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llvm-svn: 107246
2010-06-30 04:06:39 +00:00
ec0115c9b7
Add AVX SSE2 packed integer shuffle instructions
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llvm-svn: 107245
2010-06-30 03:47:56 +00:00
be792feb8b
Add AVX SSE2 pack with saturation integer instructions
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llvm-svn: 107241
2010-06-30 02:30:25 +00:00
2686ea4555
Add AVX SSE2 integer packed compare instructions
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llvm-svn: 107240
2010-06-30 02:21:09 +00:00
2e2caefff9
- Add AVX form of all SSE2 logical instructions
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- Add VEX encoding bits to x86 MRM0r-MRM7r
llvm-svn: 107238
2010-06-30 01:58:37 +00:00
3f71ddfaad
Add *several* AVX integer packed binop instructions
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llvm-svn: 107225
2010-06-29 23:47:49 +00:00
30689a3a7f
Add AVX ld/st XCSR register.
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Add VEX encoding bits for MRMXm x86 form
llvm-svn: 107204
2010-06-29 20:35:48 +00:00
a4575f5b31
Add AVX non-temporal stores
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llvm-svn: 107178
2010-06-29 18:22:01 +00:00
21a9433e9e
Add sqrt, rsqrt and rcp AVX instructions
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llvm-svn: 107166
2010-06-29 17:26:30 +00:00
d6a091a4d4
Described the missing AVX forms of SSE2 convert instructions
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llvm-svn: 107108
2010-06-29 00:36:02 +00:00
74d716b9cd
Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions
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llvm-svn: 106917
2010-06-25 23:47:23 +00:00
83651094ad
Reapply r106896:
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Add several AVX MOV flavors
Support VEX encoding for MRMDestReg
llvm-svn: 106912
2010-06-25 23:33:42 +00:00
4530fed87e
revert this now, it's using avx instead of sse :)
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llvm-svn: 106906
2010-06-25 23:04:29 +00:00
a34d9b6d84
Add several AVX MOV flavors
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Support VEX encoding for MRMDestReg
llvm-svn: 106896
2010-06-25 22:27:51 +00:00
cbdcce6478
Add some AVX convert instructions
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llvm-svn: 106815
2010-06-25 00:39:30 +00:00
4398fd7b83
- Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}.
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- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.
llvm-svn: 106787
2010-06-24 20:48:23 +00:00
8048662539
Teach the x86 mc assembler that %dr6 = %db6, this implements
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rdar://8013734
llvm-svn: 106725
2010-06-24 07:29:18 +00:00
191a1cd2bb
Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases
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llvm-svn: 106705
2010-06-24 00:32:06 +00:00
05220c9a0d
Add AVX MOVMSK{PS,PD}rr instructions
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llvm-svn: 106683
2010-06-23 21:30:27 +00:00
3183dd5692
Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction
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llvm-svn: 106678
2010-06-23 21:10:57 +00:00
360d6fe299
Add AVX SHUF{PS,PD}{rr,rm} instructions
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llvm-svn: 106672
2010-06-23 20:07:15 +00:00
337e8db712
Add support for the x86 instructions "pusha" and "popa".
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llvm-svn: 106671
2010-06-23 20:00:58 +00:00
1e13c17a55
Add AVX compare packed instructions
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llvm-svn: 106600
2010-06-22 23:37:59 +00:00
535aa8ea91
Reapply support for AVX unpack and interleave instructions, with
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testcases this time.
llvm-svn: 106593
2010-06-22 23:02:38 +00:00
1a890f9dc0
Add AVX MOV{SS,SD}{rr,rm} instructions
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llvm-svn: 106588
2010-06-22 22:38:56 +00:00
6250bd9e3c
Move a 64-bit test to the 64-bit file. Fixes an llvm-mc assertion
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during test runs.
llvm-svn: 106577
2010-06-22 21:11:51 +00:00
8737b7d73d
Refactor aliased packed logical instructions, also add
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AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.
llvm-svn: 106374
2010-06-19 02:44:01 +00:00
1e205f6b1c
Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions
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llvm-svn: 106366
2010-06-19 00:37:31 +00:00
e808a78ac1
fix rdar://7873482 by teaching the instruction encoder to emit
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segment prefixes. Daniel wrote most of this patch.
llvm-svn: 106364
2010-06-19 00:34:00 +00:00
2323168705
Add {mix,max}{ss,sd}{rr,rm} AVX forms.
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llvm-svn: 106264
2010-06-18 01:12:56 +00:00
a714ea0f7d
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rm
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llvm-svn: 105870
2010-06-12 01:53:48 +00:00
b06f54b852
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rr
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Handle OpSize TSFlag for AVX
llvm-svn: 105869
2010-06-12 01:23:26 +00:00
fd5458d4bd
More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm)
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Introduce the VEX_X field
llvm-svn: 105859
2010-06-11 23:50:47 +00:00
c2f87b7bb2
Reapply r105521, this time appending "LLU" to 64 bit
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immediates to avoid breaking the build.
llvm-svn: 105652
2010-06-08 22:51:23 +00:00
fdd2614330
revert r105521, which is breaking the buildbots with stuff like this:
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In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
llvm-svn: 105524
2010-06-05 04:17:30 +00:00
594fa26317
Initial AVX support for some instructions. No patterns matched
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yet, only assembly encoding support.
llvm-svn: 105521
2010-06-05 03:53:24 +00:00
4c71e08ed8
MC/X86: Add alias for movzx.
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llvm-svn: 105005
2010-05-28 21:20:21 +00:00
b29228905f
MC/X86: Add alias for fwait.
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llvm-svn: 105001
2010-05-28 20:59:10 +00:00
76413597a9
Fix the use of x86 control and debug registers so that the assertion failure in
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getX86RegNum() does not happen. Patch by Shantonu Sen!
llvm-svn: 104994
2010-05-28 19:01:27 +00:00
70e34983e8
Fix the x86 move to/from segment register instructions.
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llvm-svn: 104731
2010-05-26 20:10:45 +00:00
492d4f409a
Changed the encoding of X86 floating point stack operations where both operands
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are st(0). These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0. To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used. To do this the same logical trick is use from the darwin assembler
in converting things like this:
fmul %st(0), %st
into this:
fmul %st(0)
by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand. This also has the add
benefit to allow things like:
fmul %st(1), %st
that llvm-mc did not assemble.
llvm-svn: 104634
2010-05-25 20:52:34 +00:00
0e767d7364
MC/X86: Add a hack to allow recognizing 'cmpltps' and friends.
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llvm-svn: 104626
2010-05-25 19:49:32 +00:00
4a5b2c597b
MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}.
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llvm-svn: 104622
2010-05-25 18:40:53 +00:00
c798965e63
The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required
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for the 64-bit version of the Bit Test instruction.
llvm-svn: 104621
2010-05-25 18:16:58 +00:00
f6562d35ac
Make sure aeskeygenassist uses an unsigned immediate field.
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Fixes rdar://8017638
llvm-svn: 104617
2010-05-25 17:33:22 +00:00
79b6a0f140
Fix an mmx movd encoding.
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llvm-svn: 104552
2010-05-24 20:51:08 +00:00
dc71cc794b
MC/X86: Add aliases for CMOVcc variants.
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llvm-svn: 104549
2010-05-24 20:32:23 +00:00
b52fcd6304
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
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addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
llvm-svn: 104453
2010-05-22 21:02:33 +00:00
d459e29a0a
MC/X86: Add alias for setz, setnz, jz, jnz.
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llvm-svn: 104435
2010-05-22 06:37:33 +00:00
7e7482c80f
Added retl for 32-bit x86 and added retq for 64-bit x86.
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llvm-svn: 104394
2010-05-21 23:01:38 +00:00
baf2eea6f4
MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq.
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llvm-svn: 104275
2010-05-20 20:36:29 +00:00
29790edb93
Fix assembly parsing and encoding of the pushf and popf family of
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instructions.
llvm-svn: 104231
2010-05-20 16:16:00 +00:00
1e19eab963
Define the x86 pause instruction.
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llvm-svn: 104204
2010-05-20 01:35:50 +00:00
a3b7570a3a
Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it
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doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.
llvm-svn: 104203
2010-05-20 01:23:41 +00:00
7cbfa4462f
fix rdar://7986634 - match instruction opcodes case insensitively.
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llvm-svn: 104183
2010-05-19 23:34:33 +00:00
9635b3da6b
More data/parsing support for tls directives. Add a few more testcases
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and cleanup comments as well.
llvm-svn: 103985
2010-05-17 22:53:55 +00:00
9b4a824217
llvm-mc: Support reassignment of variables in one special case, when the
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variable has not yet been used in an expression. This allows us to support a few
cases that show up in real code (mostly because gcc generates it for Objective-C
on Darwin), without giving up a reasonable semantic model for assignment.
llvm-svn: 103950
2010-05-17 17:46:23 +00:00
68b1bbe66a
Assume that we'll handle mangling the symbols earlier and just put the
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symbol to the file as we have it. Simplifies out tbss handling.
llvm-svn: 103928
2010-05-17 02:13:02 +00:00
7bc111f5a9
Fix so "int3" is correctly accepted, added "into" and fixed "int" with an
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argument, like "int $4", to not get an Assertion error.
llvm-svn: 103791
2010-05-14 19:16:02 +00:00
9fb6bb07ca
Add AsmParser support for darwin tbss directive.
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Nothing uses this yet.
llvm-svn: 103757
2010-05-14 01:50:28 +00:00
8cb4728a15
fix rdar://7965971 and a fixme: use ParseIdentifier in
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ParseDirectiveDarwinZerofill instead of hard coding the
check for identifier. This allows quoted symbol names to
be used.
llvm-svn: 103682
2010-05-13 00:10:34 +00:00
9efef006cf
reapply r103668 with a fix. Never make "minor syntax changes"
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after testing before committing.
llvm-svn: 103681
2010-05-13 00:02:47 +00:00
Chris Lattner