Commit Graph

18 Commits

Author SHA1 Message Date
Dan Gohman 82656fb0e1 When sending stats output to stdout for grepping, don't emit normal
output to standard output also.

llvm-svn: 111435
2010-08-18 22:22:44 +00:00
Rafael Espindola 29dda21e96 Remove arm_apcscc from the test files. It is the default and doing this
matches what llvm-gcc and clang now produce.

llvm-svn: 106221
2010-06-17 15:18:27 +00:00
Bob Wilson 0f52d0c074 Delete dead PHI machine instructions. These can be created due to type
legalization even when the IR-level optimizer has removed dead phis, such
as when the high half of an i64 value is unused on a 32-bit target.
I had to adjust a few test cases that had dead phis.
This is a partial fix for Radar 7627077.

llvm-svn: 95816
2010-02-10 22:58:57 +00:00
Evan Cheng ea5c6be766 Run codegen dce pass for all targets at all optimization levels. Previously it's
only run for x86 with fastisel. I've found it being very effective in
eliminating some obvious dead code as result of formal parameter lowering
especially when tail call optimization eliminated the need for some of the loads
from fixed frame objects. It also shrinks a number of the tests. A couple of
tests no longer make sense and are now eliminated.

llvm-svn: 95493
2010-02-06 09:07:11 +00:00
Dan Gohman 045f81981a Revert LoopStrengthReduce.cpp to pre-r94061 for now.
llvm-svn: 94123
2010-01-22 00:46:49 +00:00
Dan Gohman 51ad99d2c5 Re-implement the main strength-reduction portion of LoopStrengthReduction.
This new version is much more aggressive about doing "full" reduction in
cases where it reduces register pressure, and also more aggressive about
rewriting induction variables to count down (or up) to zero when doing so
reduces register pressure.

It currently uses fairly simplistic algorithms for finding reuse
opportunities, but it introduces a new framework allows it to combine
multiple strategies at once to form hybrid solutions, instead of doing
all full-reduction or all base+index.

llvm-svn: 94061
2010-01-21 02:09:26 +00:00
Evan Cheng 81a2851bcb Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.
llvm-svn: 89423
2009-11-20 00:54:03 +00:00
Evan Cheng f42b5af549 Re-apply 85799. It turns out my code isn't buggy.
llvm-svn: 85947
2009-11-03 21:40:02 +00:00
Evan Cheng a8a58efc03 Revert 85799 for now. It might be breaking llvm-gcc driver.
llvm-svn: 85827
2009-11-02 21:49:14 +00:00
Evan Cheng 2729543984 Initilize the machine LICM CSE map upon the first time an instruction is hoisted to
the loop preheader. Add instructions which are already in the preheader block that
may be common expressions of those that are hoisted out. These does get a few more
instructions CSE'ed.

llvm-svn: 85799
2009-11-02 08:09:49 +00:00
Dan Gohman 50998f4584 Update this test; the code is the same but it gets counted as one
fewer remat.

llvm-svn: 83690
2009-10-09 23:31:04 +00:00
Evan Cheng 255f416470 Clean up spill weight computation. Also some changes to give loop induction
variable increment / decrement slighter high priority. 

This has major impact on some micro-benchmarks. On MultiSource/Applications
and spec tests, it's a minor win. It also reduce 256.bzip instruction count
by 8%, 55 on 164.gzip on i386 / Darwin.

llvm-svn: 82485
2009-09-21 21:12:25 +00:00
Dan Gohman c8054d90fb Eliminate more uses of llvm-as and llvm-dis.
llvm-svn: 81293
2009-09-09 00:09:15 +00:00
Evan Cheng 409c25f78d Turn on machine LICM in non-fast mode.
llvm-svn: 63855
2009-02-05 08:46:33 +00:00
Owen Anderson 252fa16db1 Remove the need for -disable-correct-folding from this test.
llvm-svn: 54354
2008-08-05 17:49:52 +00:00
Owen Anderson 5018bd032a Update these tests to work by disabling the new correct CFG generation. This flag should ONLY be used to for tests like these.
llvm-svn: 54334
2008-08-04 23:55:29 +00:00
Evan Cheng 8393dc7378 Turning simple splitting on. Start testing new coalescer heuristics as new llcbeta.
llvm-svn: 44660
2007-12-06 08:54:31 +00:00
Evan Cheng 37ed3e6320 Update tests.
llvm-svn: 44435
2007-11-29 10:03:54 +00:00