725657bad6
[SparcInstPrinter] Use the subtarget that is passed to the print function
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instead of the one passed to the constructor.
Unfortunately, I don't have a test case for this change. In order to test my
change, I will have to run the code after line 90 in printSparcAliasInstr. I
couldn't make that happen because printAliasInstr would always handle the
printing of fcmp instructions that the code after line 90 is supposed to handle.
llvm-svn: 233471
2015-03-28 04:03:51 +00:00
f9a202a9ac
[Sparc] Add VIS instructions to sparc backend.
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llvm-svn: 202660
2014-03-02 19:31:21 +00:00
ead3b3d7a1
Only generate the popc instruction for SPARC CPUs that implement it.
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The popc instruction is defined in the SPARCv9 instruction set
architecture, but it was emulated on CPUs older than Niagara 2.
llvm-svn: 200131
2014-01-26 06:09:59 +00:00
a66b314c34
[Sparc] Add missing processor types: v7 and niagara
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llvm-svn: 199024
2014-01-11 23:56:13 +00:00
c2dee7dc74
[Sparc] Add the initial implementation of an asm parser for sparc/sparcv9.
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llvm-svn: 198484
2014-01-04 11:30:13 +00:00
bf683fd15c
[Sparc] Lower and MachineInstr to MC and print assembly using MCInstPrinter.
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llvm-svn: 198030
2013-12-26 01:49:59 +00:00
50712a456d
Change the default of AsmWriterClassName and isMCAsmWriter.
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llvm-svn: 196065
2013-12-02 04:55:42 +00:00
35e0c382d5
[Sparc] Add long double (f128) instructions to sparc backend.
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llvm-svn: 189198
2013-08-25 18:30:06 +00:00
a54533ed78
Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,
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llvm-svn: 183243
2013-06-04 18:33:25 +00:00
b22310fda6
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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llvm-svn: 150878
2012-02-18 12:03:15 +00:00
72a364c107
fix emacs language spec's, patch by Edmund Grimley-Evans!
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llvm-svn: 111241
2010-08-17 16:20:04 +00:00
b93331f3be
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
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When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
llvm-svn: 100384
2010-04-05 03:10:20 +00:00
977e7be9d4
Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.
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llvm-svn: 59953
2008-11-24 07:34:46 +00:00
49b269d780
Start moving sparc to use SparcCallingConv.td, switching over
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return lowering first. This fixes a bug where the top and bottom
of i64 values were returned in the wrong registers before.
llvm-svn: 48443
2008-03-17 05:41:48 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
305c49579c
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
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llvm-svn: 28378
2006-05-18 00:12:58 +00:00
dcec882286
Remove PointerType from class Target
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llvm-svn: 28368
2006-05-17 21:20:27 +00:00
158e1f519c
Rename SPARC V8 target to be the LLVM SPARC target.
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llvm-svn: 25985
2006-02-05 05:50:24 +00:00
Akira Hatanaka