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28 Commits

Author SHA1 Message Date
Krzysztof Parzyszek b9a1c3a32c [Hexagon] Bring HexagonInstrInfo up to date 
llvm-svn: 253986
 2015-11-24 14:55:26 +00:00
Colin LeMahieu 7cd0892729 [Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing tests. General updating of the code emission. 
llvm-svn: 252443
 2015-11-09 04:07:48 +00:00
Krzysztof Parzyszek 0257905f27 [Hexagon] Change Based->Base in getBasedWithImmOffset 
llvm-svn: 250848
 2015-10-20 19:21:05 +00:00
Krzysztof Parzyszek 05da79d5ac [Hexagon] Remove the remnants of isConstExtProfitable 
llvm-svn: 250845
 2015-10-20 19:04:53 +00:00
Colin LeMahieu 7c9587136d [Hexagon] Adding skeleton of HVX extension instructions. 
llvm-svn: 250600
 2015-10-17 01:33:04 +00:00
Eric Christopher 23a7d1e6f4 Make the Hexagon ISelDAGToDAG pass set the subtarget dynamically 
on each runOnMachineFunction invocation.

llvm-svn: 232874
 2015-03-21 03:12:59 +00:00
Krzysztof Parzyszek a29622a8c5 Remove unused complex patterns for addressing modes on Hexagon. 
llvm-svn: 232057
 2015-03-12 16:44:50 +00:00
Benjamin Kramer 9d1f2dfec7 Hexagon: Remove unused InstrMapping. 
llvm-svn: 231809
 2015-03-10 18:19:16 +00:00
Colin LeMahieu 4fd203d3e1 [Hexagon] Removing more V4 predicates since V4 is the required minimum. 
llvm-svn: 228614
 2015-02-09 21:56:37 +00:00
Eric Christopher 202f22bbda Migrate HexagonISelDAGToDAG to setting a subtarget pointer during 
runOnMachineFunction. Update all uses of the Subtarget accordingly.

llvm-svn: 227840
 2015-02-02 19:22:03 +00:00
Colin LeMahieu 1445553474 [Hexagon] Adding dealloc_return encoding and absolute address stores. 
llvm-svn: 225267
 2015-01-06 16:15:15 +00:00
Colin LeMahieu 9161d47476 [Hexagon] Adding reg-reg indexed load forms. 
llvm-svn: 224997
 2014-12-30 18:58:47 +00:00
Jyotsna Verma 38901ca4f6 [Hexagon] Add new InstrItinClass to support timing classes. 
This patch doesn't introduce any functionality change. Test cases will be
added later when v5 support is added.

llvm-svn: 208349
 2014-05-08 18:47:08 +00:00
Rafael Espindola 50712a456d Change the default of AsmWriterClassName and isMCAsmWriter. 
llvm-svn: 196065
 2013-12-02 04:55:42 +00:00
Jyotsna Verma 438cec566b Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore. 
No functionality change.

llvm-svn: 181628
 2013-05-10 20:58:11 +00:00
Jyotsna Verma 300f0b966c Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp. 
llvm-svn: 181624
 2013-05-10 20:27:34 +00:00
Jyotsna Verma 84c471029b Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. 
llvm-svn: 181235
 2013-05-06 18:49:23 +00:00
Jyotsna Verma a841af7556 reverting r180953 
llvm-svn: 180964
 2013-05-02 22:10:59 +00:00
Jyotsna Verma 7e7c730c4f Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. 
llvm-svn: 180953
 2013-05-02 21:21:57 +00:00
Jyotsna Verma 5ed5181178 Hexagon: Use multiclass for Jump instructions. 
llvm-svn: 180885
 2013-05-01 21:37:34 +00:00
Jyotsna Verma efe4f559b1 Move generic Hexagon subtarget information into Hexagon.td 
llvm-svn: 169212
 2012-12-04 04:29:16 +00:00
Andrew Trick 87255e340e I'm introducing a new machine model to simultaneously allow simple 
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

llvm-svn: 159891
 2012-07-07 04:00:00 +00:00
Sirish Pande 69295b8963 Hexagon V5 FP Support. 
llvm-svn: 156568
 2012-05-10 20:20:25 +00:00
Chandler Carruth 3c3bb55a85 Revert r155365, r155366, and r155367. All three of these have regression 
test suite failures. The failures occur at each stage, and only get
worse, so I'm reverting all of them.

Please resubmit these patches, one at a time, after verifying that the
regression test suite passes. Never submit a patch without running the
regression test suite.

llvm-svn: 155372
 2012-04-23 18:25:57 +00:00
Sirish Pande a3f8ba2439 Hexagon V5 (floating point) support. 
llvm-svn: 155367
 2012-04-23 17:49:40 +00:00
Evandro Menezes 5cee621c88 Hexagon: enable assembler output through the MC layer. 
llvm-svn: 154597
 2012-04-12 17:55:53 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Tony Linthicum 1213a7a57f Hexagon backend support 
llvm-svn: 146412
 2011-12-12 21:14:40 +00:00