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6 Commits

Author SHA1 Message Date
Adrian Prantl a0852d2be3 Revert "Temporarily revert r220777 to sort out build bot breakage." 
This reverts commit r221028. Later commits depend on this and
reverting just this one causes even more bots to fail.

llvm-svn: 221041
 2014-11-01 03:19:45 +00:00
Adrian Prantl cd4872399a Temporarily revert r220777 to sort out build bot breakage. 
"[x86] Simplify vector selection if condition value type matches vselect value type and true value is all ones or false value is all zeros."

llvm-svn: 221028
 2014-11-01 00:26:59 +00:00
Robert Khasanov 4441c4d31b [x86] Simplify vector selection if condition value type matches vselect value type and true value is all ones or false value is all zeros. 
This transformation worked if selector is produced by SETCC, however SETCC is needed only if we consider to swap operands. So I replaced SETCC check for this case.
Added tests for vselect of <X x i1> values.

llvm-svn: 220777
 2014-10-28 15:59:40 +00:00
Benjamin Kramer ff8b883772 DAGCombiner: Make concat_vector combine safe for EVTs and concat_vectors with many arguments. 
PR20677

llvm-svn: 216175
 2014-08-21 13:28:02 +00:00
Elena Demikhovsky 47fc44e52e AVX-512: Added legal type MVT::i1 and VK1 register for it. 
Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.

llvm-svn: 197384
 2013-12-16 13:52:35 +00:00
Elena Demikhovsky 496656900e AVX-512: Implemented CMOV for 512-bit vectors 
llvm-svn: 193747
 2013-10-31 13:15:32 +00:00