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6 Commits

Author SHA1 Message Date
Puyan Lotfi 43e94b15ea Followup on Proposal to move MIR physical register namespace to '$' sigil. 
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
 2018-01-31 22:04:26 +00:00
Justin Bogner 6c452834a1 MIR: Print the register class or bank in vreg defs 
This updates the MIRPrinter to include the regclass when printing
virtual register defs, which is already valid syntax for the
parser. That is, given 64 bit %0 and %1 in a "gpr" regbank,

  %1(s64) = COPY %0(s64)

would now be written as

  %1:gpr(s64) = COPY %0(s64)

While this change alone introduces a bit of redundancy with the
registers block, it allows us to update the tests to be more concise
and understandable and brings us closer to being able to remove the
registers block completely.

Note: We generally only print the class in defs, but there is one
exception. If there are uses without any defs whatsoever, we'll print
the class on all uses. I'm not completely convinced this comes up in
meaningful machine IR, but for now the MIRParser and MachineVerifier
both accept that kind of stuff, so we don't want to have a situation
where we can print something we can't parse.

llvm-svn: 316479
 2017-10-24 18:04:54 +00:00
Matt Arsenault 60b91e0ba2 AMDGPU: Remove unnecessary IR from MIR tests 
llvm-svn: 307311
 2017-07-06 20:56:57 +00:00
Stanislav Mekhanoshin 286a4225b9 [AMDGPU] Fix SIFoldOperands crash with clamp 
Fixes bug #33302. Pass did not account that Src1 of max instruction
can be an immediate.

Differential Revision: https://reviews.llvm.org/D33884

llvm-svn: 304696
 2017-06-05 01:03:04 +00:00
Matt Arsenault 3cb390498e AMDGPU: Fold omod into instructions 
llvm-svn: 296372
 2017-02-27 19:35:42 +00:00
Matt Arsenault d5c6515b68 AMDGPU: Fold FP clamp as modifier bit 
The manual is unclear on the details of this. It's not
clear to me if denormals are not allowed with clamp,
or if that is only omod. Not allowing denorms for
fp16 or fp64 isn't useful so I also question if that
is really a restriction. Same with whether this is valid
without IEEE mode enabled.

llvm-svn: 295905
 2017-02-22 23:27:53 +00:00