Commit Graph

9 Commits

Author SHA1 Message Date
Sam Elliott d57de491be [RISCV] Support llvm-objdump -M no-aliases and -M numeric
Summary:
Now that llvm-objdump allows target-specific options, we match the
`no-aliases` and `numeric` options for RISC-V, as supported by GNU objdump.

This is done by overriding the variables used for the command-line options, so
that the command-line options are still supported.

This patch updates all tests using `llvm-objdump -riscv-no-aliases` to use
`llvm-objdump -M no-aliases`.

Reviewers: luismarques, asb

Reviewed By: luismarques, asb

Subscribers: pzheng, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66139

llvm-svn: 371534
2019-09-10 16:24:03 +00:00
Alex Bradbury 26403def69 [RISCV] Add UNIMP instruction (32- and 16-bit forms)
This patch adds support for UNIMP in both 32- and 16-bit forms. The 32-bit 
form can be seen as a variant of the ECALL/EBREAK/etc. family of instructions. 
The 16-bit form is just all zeroes, which isn't a valid RISC-V instruction, 
but still follows the 16-bit instruction form (i.e. bits 0-1 != 11).

Until recently unimp was undocumented and supported just by binutils, which 
printed unimp for either the 16 or 32-bit form. Both forms are now documented 
<https://github.com/riscv/riscv-asm-manual/pull/20> and binutils now supports 
c.unimp <https://sourceware.org/ml/binutils-cvs/2018-11/msg00179.html>.

Differential Revision: https://reviews.llvm.org/D54316
Patch by Luís Marques.

llvm-svn: 347988
2018-11-30 13:39:17 +00:00
Alex Bradbury fea4ac01c5 [RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands
Standardise on check lines:
* CHECK-ASM
* CHECK-OBJ
* CHECK-ASM-AND-OBJ

This allows for the addition of tests involving symbol operands, which will
not result in identical instructions in both assembly and disassembled object 
output.

This commit doesn't exploit this reworking to increase test coverage of symbol
operands - that will come in a future patch.

llvm-svn: 341546
2018-09-06 13:41:04 +00:00
Shiva Chen 7c17242b92 [RISCV] Implement c.lui immediate operand constraint
Implement c.lui immediate constraint to [1, 31] and [0xfffe0, 0xfffff].
The RISC-V ISA describes the constraint as [1, 63], with that value
being loaded in to bits 17-12 of the destination register and sign extended
from bit 17. Therefore, this 6-bit immediate can represent values in the
ranges [1, 31] and [0xfffe0, 0xfffff].

Differential Revision: https://reviews.llvm.org/D42834

llvm-svn: 325792
2018-02-22 15:02:28 +00:00
Shiva Chen 53489ada12 [RISCV] Add ELFObjectFileBase::getRISCVFeatures let llvm-objdump could get RISCV target feature
llvm-objdump could get C feature by ELF::EF_RISCV_RVC e_flag,
so then we don't have to add -mattr=+c on the command line.

Differential Revision: https://reviews.llvm.org/D42629

llvm-svn: 324058
2018-02-02 06:01:02 +00:00
Alex Bradbury 59136ffab1 [RISCV] Enable emission of alias instructions by default
This patch switches the default for -riscv-no-aliases to false
and updates all affected MC and CodeGen tests. As recommended in
D41071, MC tests use the canonical instructions and the CodeGen
tests use the aliases.

Additionally, for the f and d instructions with rounding mode,
the tests for the aliased versions are moved and tightened such
that they can actually detect if alias emission is enabled.
(see D40902 for context)

Differential Revision: https://reviews.llvm.org/D41225

Patch by Mario Werner.

llvm-svn: 320797
2017-12-15 09:47:01 +00:00
Alex Bradbury 60714f98ba [RISCV] MC layer support for the remaining RVC instructions
Differential Revision: https://reviews.llvm.org/D40003

Patch by Shiva Chen.

llvm-svn: 320558
2017-12-13 09:32:55 +00:00
Alex Bradbury f8f4b90544 [RISCV] MC layer support for the jump/branch instructions of the RVC extension
Differential Revision: https://reviews.llvm.org/D40002
    
Patch by Shiva Chen.

llvm-svn: 320038
2017-12-07 13:19:57 +00:00
Alex Bradbury 9f6aec4b7a [RISCV] MC layer support for load/store instructions of the C (compressed) extension
Differential Revision: https://reviews.llvm.org/D40001
    
Patch by Shiva Chen.

llvm-svn: 320037
2017-12-07 12:50:32 +00:00