Commit Graph

6 Commits

Author SHA1 Message Date
Luis Marques 3d0fbafd0b [RISCV] Switch to the Machine Scheduler
Most of the test changes are trivial instruction reorderings and differing
register allocations, without any obvious performance impact.

Differential Revision: https://reviews.llvm.org/D66973

llvm-svn: 372106
2019-09-17 11:15:35 +00:00
Luis Marques 2d550d19b3 Revert Patch from Phabricator
This reverts r372092 (git commit e38695a025)

llvm-svn: 372104
2019-09-17 10:52:09 +00:00
Luis Marques e38695a025 Patch from Phabricator
llvm-svn: 372092
2019-09-17 09:43:08 +00:00
Luis Marques 3091884e25 [RISCV] Add seto pattern expansion
Adds a `seto` pattern expansion. Without it the lowerings of `fcmp one` and 
`fcmp ord` would be inefficient due to an unoptimized double negation.

Differential Revision: https://reviews.llvm.org/D59699

llvm-svn: 357378
2019-04-01 09:54:14 +00:00
Alex Bradbury 7539fa2c2d [RISCV] Implement RV64D codegen
This patch:
* Adds necessary RV64D codegen patterns
* Modifies CC_RISCV so it will properly handle f64 types (with soft float ABI)

Note that in general there is no reason to try to select fcvt.w[u].d rather than fcvt.l[u].d for i32 conversions because fptosi/fptoui produce poison if the input won't fit into the target type.

Differential Revision: https://reviews.llvm.org/D53237

llvm-svn: 352833
2019-02-01 03:53:30 +00:00
Alex Bradbury 21d28fe8b8 [RISCV] Codegen support for RV32D floating point comparison operations
Also add double-prevoius-failure.ll which captures a test case that at one
point triggered a compiler crash, while developing calling convention support
for f64 on RV32D with soft-float ABI.

llvm-svn: 329877
2018-04-12 05:50:06 +00:00