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7343 Commits

Author SHA1 Message Date
Dale Johannesen da7469f2b5 Revise per review of previous patch. 
llvm-svn: 41645
 2007-08-31 17:03:33 +00:00
Rafael Espindola e636fc05d6 Initial support for calling functions with byval arguments on x86-64 
llvm-svn: 41643
 2007-08-31 15:06:30 +00:00
Rafael Espindola bb8a5cff67 Align i64 and f64 at 8 byte on x86-64. 
This is mandated table 3.1 at
http://www.x86-64.org/documentation/abi.pdf

llvm-svn: 41642
 2007-08-31 12:23:58 +00:00
Dale Johannesen 3cf889f75e Enhance APFloat to retain bits of NaNs (fixes oggenc). 
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.

llvm-svn: 41632
 2007-08-31 04:03:46 +00:00
Raul Herbster ab871baaf8 Instruction formats added used to generate multiply instructions of V5TE. 
llvm-svn: 41629
 2007-08-30 23:34:14 +00:00
Raul Herbster ff32b62942 Unused relocation type reloc_arm_absolute removed. 
llvm-svn: 41628
 2007-08-30 23:31:35 +00:00
Raul Herbster 1457b2b3b1 Comments added. It now generates V5TE multiply instructions. However, it is still necessary to model PUWLSH bits more clearly. 
llvm-svn: 41627
 2007-08-30 23:29:26 +00:00
Raul Herbster 73489273ae ARM instruction table was modified by adding information to generate multiply instruction of V5TE. 
llvm-svn: 41626
 2007-08-30 23:25:47 +00:00
Raul Herbster ae1b924c79 JITInfo now resolves function addrs and also relocations. It always emits a stub. 
llvm-svn: 41625
 2007-08-30 23:21:27 +00:00
Evan Cheng ebb8540067 Added support to fold X86 load / store instructions. This allow rematerialized loads to be folded into their uses. 
llvm-svn: 41599
 2007-08-30 05:54:07 +00:00
Evan Cheng 9a25d98c86 Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots. 
llvm-svn: 41597
 2007-08-30 05:52:20 +00:00
Evan Cheng c2081fe573 Mark load instructions with isLoad = 1. 
llvm-svn: 41595
 2007-08-30 05:49:43 +00:00
Bill Wendling 10e18dea2a Use i64 on a PPC64 machine 
llvm-svn: 41590
 2007-08-30 00:59:19 +00:00
Dale Johannesen d246b2ca5c Change LegalFPImmediates to use APFloat. 
Add APFloat interfaces to ConstantFP, SelectionDAG.
Fix integer bit in double->APFloat conversion.
Convert LegalizeDAG to use APFloat interface in
ConstantFPSDNode uses.

llvm-svn: 41587
 2007-08-30 00:23:21 +00:00
Duncan Sands 7741427a09 Move getX86RegNum into X86RegisterInfo and use it 
in the trampoline lowering.  Lookup the jump and
mov opcodes for the trampoline rather than hard
coding them.

llvm-svn: 41577
 2007-08-29 19:01:20 +00:00
Bruno Cardoso Lopes 43318839c9 Added method to get Mips register numbers 
Changed the stack frame layout, StackGrowsUp fits better to Mips strange stack.
Stack offset calculation bug fixed!

llvm-svn: 41529
 2007-08-28 05:13:42 +00:00
Bruno Cardoso Lopes 14033fb5cb Changed stack allocation On LowerFORMAL_ARGUMENTS. 
Added comments about new stack allocation.
Expand SelectCC for i32 results

llvm-svn: 41527
 2007-08-28 05:08:16 +00:00
Bruno Cardoso Lopes cfd1638e2d Mask directive completed with CalleeSave info 
Comments for Mips directives added.

llvm-svn: 41526
 2007-08-28 05:06:17 +00:00
Bruno Cardoso Lopes f55a785e56 Added methods to record SPOffsets from LowerFORMAL_ARGUMENTS 
llvm-svn: 41525
 2007-08-28 05:04:41 +00:00
Rafael Espindola b602461f48 Add a comment about using libc memset/memcpy or generating inline code. 
llvm-svn: 41502
 2007-08-27 17:48:26 +00:00
Rafael Espindola ff33241e16 call libc memcpy/memset if array size is bigger then threshold. 
Coping 100MB array (after a warmup) shows that glibc 2.6.1 implementation on
x86-64 (core 2) is 30% faster (from 0.270917s to 0.188079s)

llvm-svn: 41479
 2007-08-27 10:18:20 +00:00
Chris Lattner d8c9cb9182 rename isOperandValidForConstraint to LowerAsmOperandForConstraint, 
changing the interface to allow for future changes.

llvm-svn: 41384
 2007-08-25 00:47:38 +00:00
Chris Lattner a124f69c52 Disable EH generation until PPC works 100%. 
llvm-svn: 41360
 2007-08-24 16:00:15 +00:00
Chris Lattner 51883acec1 add a note 
llvm-svn: 41359
 2007-08-24 15:17:59 +00:00
Chris Lattner 33800d1428 add some notes on really poor codegen. 
llvm-svn: 41319
 2007-08-23 15:22:07 +00:00
Chris Lattner 92c6a65d4e new example 
llvm-svn: 41318
 2007-08-23 15:16:03 +00:00
Bill Wendling 862afea91e Add the PCSymbol for Darwin x86 platforms. 
llvm-svn: 41284
 2007-08-22 18:44:05 +00:00
Bruno Cardoso Lopes b10580ac1e InlineAsm asm support for integer registers added 
llvm-svn: 41225
 2007-08-21 16:09:25 +00:00
Bruno Cardoso Lopes d4b9945a21 Instruction Itinerary attribution fixed 
llvm-svn: 41224
 2007-08-21 16:06:45 +00:00
Anton Korobeynikov f335679b52 Use only 1 knob to enable exceptions on Darwin :). 
llvm-svn: 41208
 2007-08-21 00:31:30 +00:00
Rafael Espindola 9c3d20d823 Partial implementation of calling functions with byval arguments: 
*) The needed information is propagated to the DAG
 *) The X86-64 backend detects it and aborts

llvm-svn: 41179
 2007-08-20 15:18:24 +00:00
Chris Lattner 78846b69ae add a note 
llvm-svn: 41178
 2007-08-20 02:14:33 +00:00
Bruno Cardoso Lopes 9fbef51078 MipsHi now has ouput flag 
MipsAdd SDNode created to add support to an Add opcode which supports input flag
Added an instruction itinerary to all instruction classes
Added branches with zero cond codes
Now call clobbers all non-callee saved registers
Call w/ register support added
Added DelaySlot to branch and load instructions
Added patterns to handle all setcc, brcond/setcc and MipsAdd instructions

llvm-svn: 41161
 2007-08-18 02:37:46 +00:00
Bruno Cardoso Lopes eabe61b080 Fixed stack frame addressing bug 
llvm-svn: 41160
 2007-08-18 02:19:09 +00:00
Bruno Cardoso Lopes f3c55807f2 support for Schedule included on Mips.td 
llvm-svn: 41159
 2007-08-18 02:18:07 +00:00
Bruno Cardoso Lopes 4bd7f4db9f Removed LowerRETURADDR, fixed small bug into LowerRET, LowerGlobalAddress 
fixed to generate instructions (add, lui) glued!

llvm-svn: 41158
 2007-08-18 02:16:30 +00:00
Bruno Cardoso Lopes 833a1f9b55 Couple of small changes. Delay Slot handle header declared. 
Newline added after macros at function init on generated asm!

llvm-svn: 41157
 2007-08-18 02:05:24 +00:00
Bruno Cardoso Lopes 5792189590 Added InstrItinClass support for instruction formats 
llvm-svn: 41156
 2007-08-18 02:01:28 +00:00
Bruno Cardoso Lopes 0c530638c7 Branch Analysis and InsertNoop inserted into header files 
llvm-svn: 41155
 2007-08-18 01:59:45 +00:00
Bruno Cardoso Lopes a746512fc5 createMipsDelaySlotFillerPass added to mips codegen runtime 
llvm-svn: 41154
 2007-08-18 01:58:15 +00:00
Bruno Cardoso Lopes 7b616f5742 Added Branch Analysis support 
Added InsertNoop support

llvm-svn: 41153
 2007-08-18 01:56:48 +00:00
Bruno Cardoso Lopes e8d1c52cd4 LowerRETURNADDR removed since it was wrong and does not have utility yet! 
MipsAdd opcode added

llvm-svn: 41152
 2007-08-18 01:54:09 +00:00
Bruno Cardoso Lopes 87beec9afb InstrItineraryData support on added. 
Added Mips3 ISA feature (needed when supporting R4000 machines)

llvm-svn: 41151
 2007-08-18 01:52:27 +00:00
Bruno Cardoso Lopes 0b97ce752c A Pass to insert Nops on intructions with DelaySlot 
llvm-svn: 41150
 2007-08-18 01:50:47 +00:00
Bruno Cardoso Lopes 415ded5d5a Mips generic fallback instruction schedule support! 
llvm-svn: 41149
 2007-08-18 01:46:44 +00:00
Anton Korobeynikov 597c8b77e4 Move ReturnAddrIndex variable to X86MachineFunctionInfo structure. This fixed 
hard to catch bugs with retaddr lowering

llvm-svn: 41104
 2007-08-15 17:12:32 +00:00
Chris Lattner db8adb9941 add a note. 
llvm-svn: 41103
 2007-08-15 16:58:38 +00:00
Evan Cheng b2823dac69 Fix a typo pointd out by Maarten ter Huurne. 
llvm-svn: 41059
 2007-08-13 23:27:11 +00:00
Dan Gohman ccb3611881 When x86 addresses matching exceeds its recursion limit, check to 
see if the base register is already occupied before assuming it can be
used. This fixes bogus code generation in the accompanying testcase.

llvm-svn: 41049
 2007-08-13 20:03:06 +00:00
Chris Lattner 4e7f673f65 Fix PR1607 
llvm-svn: 41048
 2007-08-13 18:42:37 +00:00