Commit Graph

526 Commits

Author SHA1 Message Date
Tom Stellard b02094e115 R600/SI: Use scratch memory for large private arrays
llvm-svn: 213551
2014-07-21 15:45:01 +00:00
Tom Stellard 067c81567b R600/SI: Store constant initializer data in constant memory
This implements a solution for constant initializers suggested
by Vadim Girlin, where we store the data after the shader code
and then use the S_GETPC instruction to compute its address.

This saves use the trouble of creating a new buffer for constant data
and then having to pass the pointer to the kernel via user SGPRs or the
input buffer.

llvm-svn: 213530
2014-07-21 14:01:14 +00:00
Tom Stellard 54a3b65bb9 R600/SI: Use VALU for i1 XOR
llvm-svn: 213528
2014-07-21 14:01:10 +00:00
Matt Arsenault 4100ebd67b R600: Add missing test for concat_vectors
llvm-svn: 213473
2014-07-20 07:13:17 +00:00
Matt Arsenault e261b6e853 R600/SI: Remove dead code and add missing tests.
This probably was killed by some generic DAGCombiner
improvements in checking the TargetBooleanContents instead
of just 1.

llvm-svn: 213471
2014-07-20 06:11:02 +00:00
Matt Arsenault ad14ce84b7 R600/SI: implement range reduction for sin/cos
These instructions can only take a limited input range, and return
the constant value 1 out of range. We should do range reduction to
be able to process arbitrary values. Use a FRACT instruction after
normalization to achieve this. Also add a test for constant folding
with the lowered code with unsafe-fp-math enabled.

v2: use DAG lowering instead of intrinsic, adapt test
v3: calculate constant, fold pattern into instruction definition
v4: misc style fixes, add sin-fold testcase, cosmetics

Patch by Grigori Goronzy

llvm-svn: 213458
2014-07-19 18:44:39 +00:00
Tim Northover 00fdbbbf60 R600: support fpext/fptrunc operations to and from f16.
llvm-svn: 213376
2014-07-18 13:01:37 +00:00
Tim Northover 20bd0ced30 CodeGen: soften f16 type by default instead of marking legal.
Actual support for softening f16 operations is still limited, and can be added
when it's needed.  But Soften is much closer to being a useful thing to try
than keeping it Legal when no registers can actually hold such values.

Longer term, we probably want something between Soften and Promote semantics
for most targets, it'll be more efficient to promote the 4 basic operations to
f32 than libcall them.

llvm-svn: 213372
2014-07-18 12:41:46 +00:00
Tim Northover 12817862f1 R600: rename misleading fp16 test.
This test is actually going in the opposite direction to what the
filename and function name suggested.

llvm-svn: 213358
2014-07-18 08:43:30 +00:00
Tim Northover f861de3d7b R600: support f16 -> f64 conversion intrinsic.
Unfortunately, we don't seem to have a direct truncation, but the
extension can be legally split into two operations so we should
support that.

llvm-svn: 213357
2014-07-18 08:43:24 +00:00
Tim Northover fd7e424935 CodeGen: extend f16 conversions to permit types > float.
This makes the two intrinsics @llvm.convert.from.f16 and
@llvm.convert.to.f16 accept types other than simple "float". This is
only strictly needed for the truncate operation, since otherwise
double rounding occurs and there's no way to represent the strict IEEE
conversion. However, for symmetry we allow larger types in the extend
too.

During legalization, we can expand an "fp16_to_double" operation into
two extends for convenience, but abort when the truncate isn't legal. A new
libcall is probably needed here.

Even after this commit, various target tweaks are needed to actually use the
extended intrinsics. I've put these into separate commits for clarity, so there
are no actual tests of f64 conversion here.

llvm-svn: 213248
2014-07-17 10:51:23 +00:00
Matt Arsenault 22ca3f8860 R600/SI: Allow using f32 rcp / rsq when denormals not handled.
These are precise enough to use for OpenCL unless denormals
are handled.

llvm-svn: 213107
2014-07-15 23:50:10 +00:00
Matt Arsenault 0d89e849bd R600/SI: Fix select on i1
llvm-svn: 213096
2014-07-15 21:44:37 +00:00
Matt Arsenault e9fa3b8e6b R600/SI: Implement less wrong f32 fdiv
Assuming single precision denormals and accurate sqrt/div are not
reported, this passes the OpenCL conformance test.

llvm-svn: 213089
2014-07-15 20:18:31 +00:00
Jan Vesely 6ddb8dd442 R600: Implement zero undef variants of ctlz/cttz
v2: use ffbh/l if available
v3: Rebase on top of Matt's SI patches

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <tom@stellard.net>
llvm-svn: 213072
2014-07-15 15:51:09 +00:00
Matt Arsenault ca3976f7ae R600: Add dag combine for copy of an illegal type.
This helps avoid redundant instructions to unpack, and repack
the vectors. Ideally we could recognize that pattern and eliminate
it. Currently v4i8 and other small element type vectors are scalarized,
so this has the added bonus of avoiding that.

llvm-svn: 213031
2014-07-15 02:06:31 +00:00
Matt Arsenault f171cf23b8 R600: Add denormal handling subtarget features.
llvm-svn: 213018
2014-07-14 23:40:49 +00:00
Matt Arsenault c6ae7b4763 R600/SI: Default to no single precision denormals.
llvm-svn: 213017
2014-07-14 23:40:43 +00:00
Matt Arsenault 7d5e2cb09f R600: Run more tests with promote alloca disabled.
Re-run tests changed in r211110 to test both paths.
Also fix broken check line.

llvm-svn: 212895
2014-07-13 02:46:17 +00:00
Matt Arsenault d0b6f3e173 R600: Run private-memory test with and without alloca promote
The unpromoted path still needs to be tested since we can't
always promote to using LDS.

llvm-svn: 212894
2014-07-13 02:18:06 +00:00
Matt Arsenault 6026858158 R600: Add missing tests for some intrinsics
llvm-svn: 212870
2014-07-12 00:36:19 +00:00
Marek Olsak eac5062cc0 R600/SI: Use i32 vectors for resources and samplers
This affects new intrinsics only.

What surprises me is that v32i8 still works.

llvm-svn: 212831
2014-07-11 17:11:52 +00:00
Marek Olsak d8ecaeec02 R600/SI: add sample and image intrinsics exposing all instruction fields
We need the intrinsics with offsets, so why not just add them all.
The R128 parameter will also be useful for reducing SGPR usage.
GL_ARB_image_load_store also adds some image GLSL modifiers like "coherent",
so Mesa will probably translate those to slc, glc, etc.

When LLVM 3.5 is released, I'll switch Mesa to these new intrinsics.

llvm-svn: 212830
2014-07-11 17:11:46 +00:00
Jan Vesely 2cb62ce2a0 R600: Implement float to long/ulong
Use alg. from LegalizeDAG.cpp
Move Expand setting to SIISellowering

v2: Extend existing tests instead of creating new ones
v3: use separate LowerFPTOSINT function
v4: use TargetLowering::expandFP_TO_SINT
    add comment about using FP_TO_SINT for uints

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <tom@stellard.net>
llvm-svn: 212773
2014-07-10 22:40:21 +00:00
Matt Arsenault 3332b70627 Revert "Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine.""
Don't try to convert the select condition type.

llvm-svn: 212750
2014-07-10 18:21:04 +00:00
NAKAMURA Takumi f862ce8908 Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine."
This caused miscompilation on, at least, x86-64. SExt(i1 cond) confused other optimizations.

llvm-svn: 212708
2014-07-10 11:37:28 +00:00
Matt Arsenault b0df92577d R600/SI: Add support for llvm.convert.{to|from}.fp16
llvm-svn: 212676
2014-07-10 03:22:20 +00:00
Matt Arsenault 658c5576d1 Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine.
Do this if the truncate is free and the select is legal.

llvm-svn: 212640
2014-07-09 19:12:07 +00:00
Matt Arsenault d2c9e08b63 R600: Fix mishandling of load / store chains.
Fixes various bugs with reordering loads and stores.
Scalarized vector loads weren't collecting the chains
at all.

llvm-svn: 212473
2014-07-07 18:34:45 +00:00
Tom Stellard 10ae6a0e6a R600: Promote i64 loads to v2i32
llvm-svn: 212216
2014-07-02 20:53:54 +00:00
Matt Arsenault 018e91f808 Revert "Temporary hack to try cleaning extra .s file from bots."
llvm-svn: 211967
2014-06-27 23:11:26 +00:00
Matt Arsenault c9c44d682c Temporary hack to try cleaning extra .s file from bots.
llvm-svn: 211963
2014-06-27 21:43:50 +00:00
David Blaikie 6a21e14d53 Fix test so it doesn't try to write out temporary files into the test tree.
llvm-svn: 211916
2014-06-27 17:45:43 +00:00
Matt Arsenault 642d2e78b3 R600: Don't crash on unhandled instruction in promote alloca
llvm-svn: 211906
2014-06-27 16:52:49 +00:00
Matt Arsenault 6995dd90c0 R600: Add some testcases for promote alloca pass.
More complicated GEPs are skipped. Add some tests to
actually stress this skipping.

llvm-svn: 211859
2014-06-27 03:55:55 +00:00
Matt Arsenault 0989d51520 R600/SI: Add FP mode bits to binary.
The default rounding mode to initialize the mode register needs
to be reported to the runtime. Fill in other bits a kernel
may be interested in setting for future use.

llvm-svn: 211791
2014-06-26 17:22:30 +00:00
Matt Arsenault c6f8fdb4e5 R600: Fix vector FMA
llvm-svn: 211757
2014-06-26 01:28:05 +00:00
Tom Stellard 9b3816b5ee R600: Promote i64 stores to v2i32
Now we need only one 64-bit pattern for stores.

llvm-svn: 211643
2014-06-24 23:33:04 +00:00
Matt Arsenault 257d48d22c R600: Fix inconsistency in rsq instructions.
R600 was using a clamped version of rsq, but SI was not. Add a
new rsq_clamped intrinsic and use them consistently.

It's unclear to me from the documentation what behavior
the R600 instructions have, so I assume they have the legacy behavior
described by the SI documents. For R600, use RECIPSQRT_IEEE
for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also
has RECIPSQRT_FF, which I'm not sure how it fits in here.

llvm-svn: 211637
2014-06-24 22:13:39 +00:00
Matt Arsenault f2b0aebb8a R600/SI: Fix div_scale intrinsic.
The operand that must match one of the others does matter,
and implement selecting for it.

llvm-svn: 211523
2014-06-23 18:28:28 +00:00
Matt Arsenault c4d3d3a16e R600: Move add/sub with overflow out of AMDILISelLowering
Add more tests for these.

llvm-svn: 211517
2014-06-23 18:00:49 +00:00
Matt Arsenault b8b5153935 R600/SI: Handle i64 sub.
We can handle it the same way as add

llvm-svn: 211514
2014-06-23 18:00:38 +00:00
Jan Vesely b32714054a R600: Add udivrem test
v2: move < %s to the end of the line
    space after ;
    add v4i32 test

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211476
2014-06-22 21:42:58 +00:00
Tom Stellard ae4c9e7bc3 R600/SI: Add patterns for ctpop inside a branch
llvm-svn: 211378
2014-06-20 17:06:11 +00:00
Tom Stellard 9c603ebca4 R600/SI: Add a pattern for f32 ftrunc
llvm-svn: 211377
2014-06-20 17:06:09 +00:00
Tom Stellard a79e9f0f6d R600: Expand vector flog2
llvm-svn: 211376
2014-06-20 17:06:07 +00:00
Tom Stellard 5222a88653 R600: Expand vector fexp2
llvm-svn: 211375
2014-06-20 17:06:05 +00:00
Tom Stellard c9dedb8e29 R600/SI: Add a VALU pattern for i64 xor
llvm-svn: 211373
2014-06-20 17:05:57 +00:00
Matt Arsenault 8e34ecb797 R600: Add a few tests I forgot to add.
These belong with r210827

llvm-svn: 211253
2014-06-19 04:24:43 +00:00
Matt Arsenault a0050b0961 R600/SI: Add intrinsics for various math instructions.
These will be used for custom lowering and for library
implementations of various math functions, so it's useful
to expose these as builtins.

llvm-svn: 211247
2014-06-19 01:19:19 +00:00