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278459 Commits

Author SHA1 Message Date
Davide Italiano d752d6b4be [DataEncoder] Replace buggy versions of write functions. 
They cause an ubsan error when ran through the testsuite (store
to misaligned address is UB). This commit kills two birds with
one stone, as we also remove some code while fixing it.

<rdar://problem/35941757>

llvm-svn: 320335
 2017-12-10 22:54:07 +00:00
Simon Pilgrim 6b1f532ccf [X86] Add ROL/ROR schedule tests 
llvm-svn: 320334
 2017-12-10 22:11:56 +00:00
Simon Pilgrim a6564e2358 [X86] Add DIV/MUL/NEG/NOP/NOT/PAUSE schedule tests 
llvm-svn: 320333
 2017-12-10 21:56:24 +00:00
Simon Pilgrim 8e6d0fcbac [X86] Add DEC/INC schedule tests 
Include i686 (non-REX) variant tests as well

llvm-svn: 320332
 2017-12-10 21:28:00 +00:00
Simon Pilgrim f1c51d187a [X86] Add INS/OUTS schedule tests 
llvm-svn: 320331
 2017-12-10 21:10:28 +00:00
Simon Pilgrim 07ebbd53f0 [X86] Add CMPS/MOVS/SCAS/STOS schedule tests 
llvm-svn: 320330
 2017-12-10 20:58:22 +00:00
Simon Pilgrim f65831d731 [X86] Add CMOV schedule tests 
llvm-svn: 320329
 2017-12-10 20:46:57 +00:00
Simon Pilgrim 4a431edddc [X86] Add BT/BTC/BTR/BTS schedule tests 
llvm-svn: 320328
 2017-12-10 20:22:47 +00:00
Rafael Espindola 87e0deaea7 Move RelaPlt and RelaIplt to InX. NFC. 
llvm-svn: 320327
 2017-12-10 20:07:03 +00:00
Craig Topper c6a4a97260 [X86] Add VCOMISDZrr, VCOMISSZrr, VUCOMISDZrr, and VUCOMISSZrr to the skylake server sheduler model 
llvm-svn: 320326
 2017-12-10 19:47:57 +00:00
Craig Topper a0be5a06c1 [X86] Rename some instructions that start with Int_ to have the _Int at the end. 
This matches AVX512 version and is more consistent overall. And improves our scheduler models.

In some cases this adds _Int to instructions that didn't have any Int_ before. It's a side effect of the adjustments made to some of the multiclasses.

llvm-svn: 320325
 2017-12-10 19:47:56 +00:00
Rafael Espindola 58946cdb08 Move RelaDyn to InX. NFC. 
llvm-svn: 320324
 2017-12-10 19:44:42 +00:00
Rafael Espindola 6d907105c5 Remove this->. NFC. 
llvm-svn: 320323
 2017-12-10 19:28:32 +00:00
Simon Pilgrim c493d4f5b9 [X86][X87] Fix typo in znver1 FIST/FISTT schedule patterns 
llvm-svn: 320322
 2017-12-10 19:19:22 +00:00
Simon Pilgrim 930e435937 [X86][X87] Add missing x87 scheduler tests 
Split off some 'n' instruction versions to make it clearer when WAIT is being inserted

llvm-svn: 320321
 2017-12-10 18:53:15 +00:00
Craig Topper 1de942b2d1 [X86] Rename some instructions from 'rb' to 'rrb' to make 'b' a proper suffix. Fix the scheduling information for some of them. 
Some of the scheduling information was only present for the 'rb' version' and not the 'rr' version. Now we match 'rr(b?)'

llvm-svn: 320320
 2017-12-10 17:42:44 +00:00
Craig Topper c7445f2cdc [X86] Add VCVTQQ2PS to the skylake server scheduler models. 
llvm-svn: 320319
 2017-12-10 17:42:43 +00:00
Craig Topper c268527b2f [X86] Add VPMULLWZ256 to the skylake server scheduler model 
llvm-svn: 320318
 2017-12-10 17:42:42 +00:00
Craig Topper 4ec397cbd3 [X86] Add 256/512-bit EVEX VPSADBW instructions to skylake server scheduler model. 
llvm-svn: 320317
 2017-12-10 17:42:41 +00:00
Craig Topper aa904d5ab6 [X86] Fix a few instructions that were named Z512 instead of just Z. 
This makes things consistent with our normal instruction naming.

llvm-svn: 320316
 2017-12-10 17:42:39 +00:00
Craig Topper 7c89de1760 [X86] Add VPSRLWZrr to skylake server scheduler model. 
llvm-svn: 320315
 2017-12-10 17:42:38 +00:00
Craig Topper 1d7760db49 [X86] Add VPUNPCKLWDZrr to skylake server scheduler model. 
llvm-svn: 320314
 2017-12-10 17:42:37 +00:00
Craig Topper 57c2815cbe [X86] Adjust tablegen includes so we can use Instructions in scheduler models instead of just instregexs. 
This separates the CPU specific scheduler model includes to occur after the instructions. Moves the instruction includes between the basic scheduler information and the CPU specific scheduler models.

llvm-svn: 320313
 2017-12-10 17:42:36 +00:00
Sanjay Patel b23e148114 [SimplifyLibCalls] propagate FMF when folding pow(x, -1.0) call 
Follow-up for a bug that's similar to:
https://bugs.llvm.org/show_bug.cgi?id=35601

llvm-svn: 320312
 2017-12-10 17:25:54 +00:00
Sanjay Patel ac9cbd6c56 [InstCombine] add test for pow(x, -1.0) with FMF; NFC 
llvm-svn: 320311
 2017-12-10 17:21:51 +00:00
Sanjay Patel 09ec34349a [SimplifyLibCalls] propagate FMF when folding pow(x, 2.0) call (PR35601) 
This should fix the larger problem with sqrt shown in:
https://bugs.llvm.org/show_bug.cgi?id=35601

llvm-svn: 320310
 2017-12-10 16:52:26 +00:00
Sanjay Patel 719bc64ba5 [InstCombine] add test for pow(x, 2.0) with FMF; NFC 
llvm-svn: 320309
 2017-12-10 16:43:34 +00:00
Simon Pilgrim 1f8cfba0bb [X86] Flag BroadWell scheduler model as complete 
Locally tag COPY as WriteMove, which has caused some reg-reg + reg-mem instruction tests to reorder.

llvm-svn: 320308
 2017-12-10 13:49:51 +00:00
Simon Pilgrim 4ff43d8120 Regenerate some AVX2+ scheduling tests that got missed 
llvm-svn: 320307
 2017-12-10 13:41:29 +00:00
Simon Pilgrim 49c74934dd Strip trailing whitespace. NFCI. 
llvm-svn: 320306
 2017-12-10 13:00:37 +00:00
Simon Pilgrim af35b76bda Regenerate some scheduling tests that got missed 
llvm-svn: 320305
 2017-12-10 12:59:55 +00:00
Simon Pilgrim 320996576d [X86] Flag ZNVER1 scheduler model as complete 
We just have to locally tag COPY as WriteMove

llvm-svn: 320304
 2017-12-10 12:43:53 +00:00
Simon Pilgrim 8547645948 [X86] Flag SLM scheduler model as complete 
We just have to locally tag COPY as WriteMove

llvm-svn: 320303
 2017-12-10 12:36:29 +00:00
Simon Pilgrim 91c159d841 [X86][AVX[ Tag VZEROALL/VZEROUPPER instructions scheduler classes 
llvm-svn: 320302
 2017-12-10 12:26:35 +00:00
Simon Pilgrim 6de94a1adc [X86] Tag SSE4A instructions as SSE INTALU scheduler classes 
llvm-svn: 320301
 2017-12-10 12:08:04 +00:00
Simon Pilgrim cd58171110 [X86] Flag BTVER2 scheduler model as complete 
We just have to locally tag COPY as WriteMove

llvm-svn: 320300
 2017-12-10 11:51:29 +00:00
Simon Pilgrim b7fb2e2fa1 [X86] Tag ADJSTACK instructions as INTALU scheduler class 
llvm-svn: 320299
 2017-12-10 11:34:08 +00:00
Dorit Nuzman 5809e70540 [SCEV] Fix wrong Equal predicate created in getAddRecForPhiWithCasts 
CreateAddRecFromPHIWithCastsImpl() adds an IncrementNUSW overflow predicate
which allows the PSCEV rewriter to rewrite this scev expression:
 (zext i8 {0, + , (trunc i32 step to i8)} to i32)
into
 {0, +, (sext i8 (trunc i32 step to i8) to i32)}

But then it adds the wrong Equal predicate:
 %step == (zext i8 (trunc i32 %step to i8) to i32).
instead of:
 %step == (sext i8 (trunc i32 %step to i8) to i32)

This is fixed here.

Differential Revision: https://reviews.llvm.org/D40641

llvm-svn: 320298
 2017-12-10 11:13:35 +00:00
Simon Pilgrim d038b475ac Fix MSVC 'not all control paths return a value' warning 
llvm-svn: 320297
 2017-12-10 11:05:14 +00:00
Simon Pilgrim 1a030016a6 [X86] Tag MORESTACK instructions as ret scheduler class 
llvm-svn: 320296
 2017-12-10 10:08:21 +00:00
Craig Topper 253562eb81 [X86] Fix duplicate entries in skylake server scheduler model by changing Z128 to Z256 
Based on the fact that the 'Y' version of the instruction is next to this, I assume Z256 is the intended value.

llvm-svn: 320295
 2017-12-10 09:14:45 +00:00
Craig Topper 90c9c15936 [X86] Add MOVQI2PQIrm, MOVSDmr, and MOVSDrm to scheduler information 
The VEX versions were present but not the legacy SSE versions.

llvm-svn: 320294
 2017-12-10 09:14:44 +00:00
Craig Topper 28e55386ac [X86] Add LEA64_32r to scheduler models for Sandybridge,Haswell,Broadwell,Skylake 
llvm-svn: 320293
 2017-12-10 09:14:42 +00:00
Craig Topper 8ade4640f3 [X86] Add IN16/OUT16 to scheduling information for Haswell,Broadwell,Skylake 
Sandy Bridge is also missing it, but it has other issues. See PR35590.

llvm-svn: 320292
 2017-12-10 09:14:41 +00:00
Craig Topper 1a88c50fd7 [X86] Fix scheduler models to support ADD32ri in addition to ADD32ri8. Similar for all sizes of AND/OR/XOR/SUB/ADC/SBB/CMP. 
llvm-svn: 320291
 2017-12-10 09:14:39 +00:00
Craig Topper c89e282f7d [X86] Rename some instructions so that 'b' is added as a suffix instead of replacing an 'r' 
llvm-svn: 320290
 2017-12-10 09:14:38 +00:00
Craig Topper 6c65910160 [X86] Add CMPSDrr/rm to the scheduler models. 
Somehow CMPSSrr/rm was there and the VEX version was there, but this was consistently missing.

llvm-svn: 320289
 2017-12-10 09:14:37 +00:00
Craig Topper d435a1950f [Docs] Fix typo in scheduler model documentation. enumemation->enumeration 
llvm-svn: 320288
 2017-12-10 09:14:35 +00:00
Tim Northover cf4701bb89 PowerPC: support external pid instructions in MC layer. 
This adds assembly & disassembly support for the e500mc "external pid"
instructions.

See https://reviews.llvm.org/D39249.

Patch by vit9696 <vit9696@avp.su>

llvm-svn: 320287
 2017-12-10 08:43:19 +00:00
Tim Northover 8f1bc370e2 PPC32: Support R_PPC_PLTREL32 in static mode. 
See https://reviews.llvm.org/D39226

Patch by vit9696 <vit9696@avp.su>

llvm-svn: 320286
 2017-12-10 08:42:34 +00:00