9a278bf6b5
Revert "AMDGPU/NFC: Cleanup subtarget predicates"
...
It breaks one of our downstream merges, so revert it
temporarily while investigating failures downstream
llvm-svn: 354700
2019-02-22 23:21:06 +00:00
c2650178a1
AMDGPU/NFC: Cleanup subtarget predicates
...
Differential Revision: https://reviews.llvm.org/D58522
llvm-svn: 354620
2019-02-21 20:43:43 +00:00
79b5c3842b
AMDGPU/GlobalISel: Move SMRD selection logic to TableGen
...
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: volkan, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D52922
llvm-svn: 354516
2019-02-20 21:02:37 +00:00
2946cd7010
Update the file headers across all of the LLVM projects in the monorepo
...
to reflect the new license.
We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.
Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.
llvm-svn: 351636
2019-01-19 08:50:56 +00:00
14d8807d9a
AMDGPU/GlobalISel: Select amdgcn.cvt.pkrtz to 64-bit instructions
...
Summary: The 32-bit variants do not exist on VI+.
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D52958
llvm-svn: 343985
2018-10-08 17:49:29 +00:00
ac68471326
AMDGPU/GlobalISel: Implement select() for 32-bit @llvm.minnun and @llvm.maxnum
...
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D46172
llvm-svn: 337056
2018-07-13 22:16:03 +00:00
26fac0f8e1
AMDGPU/GlobalISel: legalize and select 32-bit G_ASHR
...
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D48196
llvm-svn: 335318
2018-06-22 02:54:57 +00:00
9a6535718e
AMDGPU/GlobalISel: legalize and select 32-bit G_SITOFP
...
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D48195
llvm-svn: 335316
2018-06-22 02:34:29 +00:00
a92847359a
AMDGPU/GlobalISel: Implement select() for @llvm.amdgcn.cvt.pkrtz
...
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45907
llvm-svn: 334757
2018-06-14 19:26:37 +00:00
46bbbc33c0
AMDGPU/GlobalISel: Implement select() for 32-bit G_FADD and G_FMUL
...
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D46171
llvm-svn: 334665
2018-06-13 22:30:47 +00:00
dcc95e9385
AMDGPU/GlobalISel: Implement select() for 32-bit G_FPTOUI
...
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45883
llvm-svn: 332082
2018-05-11 05:44:16 +00:00
1dc90204bf
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
...
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-10 20:53:06 +00:00
Konstantin Zhuravlyov