llvm-project

Commit Graph

Author	SHA1	Message	Date
Reid Kleckner	89b57061f7	Move TargetRegistry.(h\|cpp) from Support to MC This moves the registry higher in the LLVM library dependency stack. Every client of the target registry needs to link against MC anyway to actually use the target, so we might as well move this out of Support. This allows us to ensure that Support doesn't have includes from MC/*. Differential Revision: https://reviews.llvm.org/D111454	2021-10-08 14:51:48 -07:00
Scott Linder	bd12ecb88f	[AMDGPU] Fix PC register mapping in wave32 mode Summary: The PC_32 DWARF register is for a 32-bit process address space which we don't implement in AMDGCN; another way of putting this is that the size of the PC register is not a function of the wavefront size. If we ever implement a 32-bit process address space we will need to add two more DwarfFlavours i.e. we will need to represent the product of (wave32, wave64) x (64-bit address space, 32-bit address space). Tags: #llvm Differential Revision: https://reviews.llvm.org/D76732	2020-03-26 14:43:25 -04:00
Ram Nalamothu	24698e526f	Implement wave32 DWARF register mapping Implement the DWARF register mapping described in llvm/docs/AMDGPUUsage.rst. This enables generating appropriate DWARF register numbers for wave64 and wave32 modes.	2020-03-23 10:24:16 -04:00

Author

SHA1

Message

Date

Reid Kleckner

89b57061f7

Move TargetRegistry.(h|cpp) from Support to MC

This moves the registry higher in the LLVM library dependency stack.
Every client of the target registry needs to link against MC anyway to
actually use the target, so we might as well move this out of Support.

This allows us to ensure that Support doesn't have includes from MC/*.

Differential Revision: https://reviews.llvm.org/D111454

2021-10-08 14:51:48 -07:00

Scott Linder

bd12ecb88f

[AMDGPU] Fix PC register mapping in wave32 mode

Summary:
The PC_32 DWARF register is for a 32-bit process address space which we
don't implement in AMDGCN; another way of putting this is that the size
of the PC register is not a function of the wavefront size. If we ever
implement a 32-bit process address space we will need to add two more
DwarfFlavours i.e. we will need to represent the product of (wave32,
wave64) x (64-bit address space, 32-bit address space).

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76732

2020-03-26 14:43:25 -04:00

Ram Nalamothu

24698e526f

Implement wave32 DWARF register mapping

Implement the DWARF register mapping described in llvm/docs/AMDGPUUsage.rst.

This enables generating appropriate DWARF register numbers for wave64 and
wave32 modes.

2020-03-23 10:24:16 -04:00

3 Commits