2756dc17a6
Add an OutPatFrag TableGen class
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Unfortunately, it is currently impossible to use a PatFrag as part of an output
pattern (the part of the pattern that has instructions in it) in TableGen.
Looking at the current implementation, this was clearly intended to work (there
is already code in place to expand patterns in the output DAG), but is
currently broken by the baked-in type-checking assumption and the order in which
the pattern fragments are processed (output pattern fragments need to be
processed after the instruction definitions are processed).
Fixing this is fairly simple, but requires some way of differentiating output
patterns from the existing input patterns. The simplest way to handle this
seems to be to create a subclass of PatFrag, and so that's what I've done here.
As a simple example, this allows us to write:
def crnot : OutPatFrag<(ops node:$in),
(CRNOR $in, $in)>;
def : Pat<(not i1:$in),
(crnot $in)>;
which captures the core use case: handling of repeated subexpressions inside
of complicated output patterns.
This will be used by an upcoming commit to the PowerPC backend.
llvm-svn: 202450
2014-02-28 00:26:56 +00:00
8b88da45da
Fix indentation.
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llvm-svn: 202344
2014-02-27 03:30:36 +00:00
e413b628f8
[x86] Simplify disassembler code slightly.
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llvm-svn: 202233
2014-02-26 06:01:21 +00:00
c95bd8d88f
Stackmaps are used for OSR exits, which is a custom kind of unwinding. Hence, they
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should not be marked nounwind.
Marking them nounwind caused crashes in the WebKit FTL JIT, because if we enable
sufficient optimizations, LLVM starts eliding compact_unwind sections (or any unwind
data for that matter), making deoptimization via stackmaps impossible.
This changes the stackmap intrinsic to be may-throw, adds a test for exactly the
sympton that WebKit saw, and fixes TableGen to handle un-attributed intrinsics.
Thanks to atrick and philipreames for reviewing this.
llvm-svn: 201826
2014-02-20 23:57:31 +00:00
e2347df24d
[x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. Remove HasREPPrefix support from disassembler table generator since its now only used by CodeGenOnly instructions.
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llvm-svn: 201767
2014-02-20 07:59:43 +00:00
56f0ed815e
Remove special FP opcode maps and instead add enough MRM_XX formats to handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change.
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llvm-svn: 201649
2014-02-19 08:25:02 +00:00
2fb696b214
Put some of the X86 formats in a more logical order.
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llvm-svn: 201645
2014-02-19 06:59:13 +00:00
0d1fd55c13
Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.
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llvm-svn: 201641
2014-02-19 05:34:21 +00:00
ea09c595a6
Rename a DebugLoc variable to DbgLoc and a DataLayout to DL.
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This is quiet a bit less confusing now that TargetData was renamed DataLayout.
llvm-svn: 201606
2014-02-18 22:05:46 +00:00
5ccb61781f
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler.
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llvm-svn: 201538
2014-02-18 00:21:49 +00:00
7aaa0c2ddb
Remove unused method declaration.
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llvm-svn: 201301
2014-02-13 07:12:40 +00:00
69e245c01d
Remove filtering concept from X86 disassembler table generation. It's no longer necessary.
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llvm-svn: 201299
2014-02-13 07:07:16 +00:00
5b3a6bd370
Remove special case filtering for instructions with lock prefix as they are all marked with isCodeGenOnly already.
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llvm-svn: 201216
2014-02-12 08:09:20 +00:00
ea91f02762
Mark XACQUIRE_PREFIX/XRELEASE_PREFIX as isAsmParserOnly so they'll disappear from the disassembler table build without custom filtering code.
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llvm-svn: 201215
2014-02-12 08:02:29 +00:00
a0869dceea
Recommit r201059 and r201060 with hopefully a fix for its original failure.
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Original commits messages:
Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code.
Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information.
llvm-svn: 201065
2014-02-10 06:55:41 +00:00
ebdae7c2ff
Revert r201059 and r201060.
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r201059 appears to cause a crash in a bootstrapped build of clang. Craig
isn't available to look at it right now, so I'm reverting it while he
investigates.
llvm-svn: 201064
2014-02-10 05:28:30 +00:00
0a43c2c393
Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information.
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llvm-svn: 201060
2014-02-10 01:58:12 +00:00
0d88de8c56
Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code.
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llvm-svn: 201059
2014-02-10 00:50:34 +00:00
2813e3a46e
Remove unnecessary include.
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llvm-svn: 201041
2014-02-09 07:55:19 +00:00
31afdb8c26
Remove some unnecessary code. The conditions it was checking had already been ruled out by the caller.
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llvm-svn: 201039
2014-02-09 07:13:41 +00:00
1dc1034218
LLVM-1163: AAPCS-VFP violation when CPRC allocated to stack
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According to the AAPCS, when a CPRC is allocated to the stack, all other
VFP registers should be marked as unavailable.
I have also modified the rules for allocating non-CPRCs to the stack, to make
it more explicit that all GPRs must be made unavailable. I cannot think of a
case where the old version would produce incorrect answers, so there is no test
for this.
llvm-svn: 200970
2014-02-07 11:19:53 +00:00
f1aab4502e
Delete all of the CodeGenInstructions from CodeGenTarget destructor.
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llvm-svn: 200906
2014-02-06 06:27:59 +00:00
bc9486bea0
Shrink the size of CodeGenInstruction a little bit by using bitfields. 32 bools seemed excessive.
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llvm-svn: 200829
2014-02-05 09:10:40 +00:00
4c6129af32
Get rid of a vector copy by just making a pointer out of the reference returned by getInstructionsByEnumValue instead of assigning it to a new vector.
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llvm-svn: 200828
2014-02-05 07:56:49 +00:00
65efcb4685
Fix a vector that was passed by value instead of reference.
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llvm-svn: 200827
2014-02-05 07:27:49 +00:00
1129d452cd
Fix a doxygen comment referencing the wrong method name.
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llvm-svn: 200825
2014-02-05 07:21:07 +00:00
7ca1d18055
Add CheckChildInteger to ISelMatcher operations. Removes nearly 2000 bytes from X86 matcher table.
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llvm-svn: 200821
2014-02-05 05:44:28 +00:00
d8dd194f03
TableGen/X86RecognizableInstr.h: Prune out-of-date "@param isSSE". [-Wdocumentation]
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llvm-svn: 200628
2014-02-02 10:53:36 +00:00
fa6298a162
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64.
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llvm-svn: 200626
2014-02-02 09:25:09 +00:00
8e92e85ac7
Simplify some code since VEX and EVEX instructions never have HasOpSizePrefix.
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llvm-svn: 200625
2014-02-02 07:46:05 +00:00
d402df3ce8
Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags.
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llvm-svn: 200624
2014-02-02 07:08:01 +00:00
10243c8907
Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters.
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llvm-svn: 200522
2014-01-31 08:47:06 +00:00
ec68866f55
Move REP out of the Prefix field of the X86 format. Give it its own bit. It had special handling anyway and this enables a future patch.
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llvm-svn: 200520
2014-01-31 07:00:55 +00:00
bdf33ca08d
Couple minor formatting fixes to the XXXGenDAGISel.inc files.
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llvm-svn: 200459
2014-01-30 06:42:52 +00:00
0d16d2dc31
Delete the Matchers stored in the SmallVectors in SwitchOpcodeMatcher/SwitchTypeMatcher.
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llvm-svn: 200377
2014-01-29 07:06:07 +00:00
3fa98a65e9
Propagate MCSubtargetInfo through TableGen's getBinaryCodeForInstr()
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llvm-svn: 200349
2014-01-28 23:13:18 +00:00
e6c13e4abd
Change MCStreamer EmitInstruction interface to take subtarget info
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llvm-svn: 200345
2014-01-28 23:12:42 +00:00
74169dcf45
Improve handling of EnforceSmallerThan. Remove all types that are smaller from the larger set not just the smallest type from the smaller set. Ensure 'smaller' vectors have the same or fewer total bits. Similar for 'larger' vectors.
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llvm-svn: 200287
2014-01-28 04:49:01 +00:00
6e1faaf886
Don't use EnforceSmallerThan for EnforceVectorSubVectorTypeIs. EnforceSmallerThan doesn't handle vectors quite right and should really enforce that vectors have the same number of elements. Add explicit checks for vector element count differing in EnforceVectorSubVectorTypeIs instead. This removes some unnecessary type checks in X86GenDAGISel.inc.
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llvm-svn: 200091
2014-01-25 17:40:33 +00:00
336e1f1179
Fix typo in commment tyep->type.
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llvm-svn: 200089
2014-01-25 17:34:23 +00:00
5f730e8ef1
Use isConcrete and getConcrete instead of using TypeVec directly.
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llvm-svn: 200071
2014-01-25 05:33:48 +00:00
6dbcb945a2
Fix EnforceSmallerThan to check !hasVectorTypes on the other type instead of this type to force this type to be scalar.
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llvm-svn: 200070
2014-01-25 05:17:38 +00:00
3f9978e65a
Remove TGValueTypes.cpp from CMakeLists.txt which I forgot to do in r200036.
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llvm-svn: 200037
2014-01-24 20:51:32 +00:00
8561de90d7
Replace tablegen uses of EVT with MVT. Add isOverloaded() to MVT to facilitate. Remove TGValueTypes.cpp since its unused now (and may have been before).
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llvm-svn: 200036
2014-01-24 20:50:47 +00:00
cb40291100
Fix known typos
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Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.
llvm-svn: 200018
2014-01-24 17:20:08 +00:00
9bbf7ca13d
]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)
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llvm-svn: 199806
2014-01-22 15:08:36 +00:00
b33c2ef215
[x86] Allow address-size overrides for STOS[BWLQ] (PR9385)
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llvm-svn: 199804
2014-01-22 15:08:21 +00:00
2ef8d9c05c
[x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)
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llvm-svn: 199803
2014-01-22 15:08:08 +00:00
a2c60197bf
Use ArrayRef to simplify some code.
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llvm-svn: 199712
2014-01-21 07:20:05 +00:00
caaa2850c0
[x86] Fix disassembly of MOV16ao16 et al.
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The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.
llvm-svn: 199654
2014-01-20 12:02:53 +00:00
Hal Finkel