llvm-project

Commit Graph

Author	SHA1	Message	Date
Hsiangkai Wang	6e360460f1	[RISCV] Use v8-v23 as argument registers to conform to the proposal. The maximum LMUL is 8. We need 16 vector registers for two LMUL-8 arguments. The modification follows the proposal of psABI in https://github.com/riscv/riscv-elf-psabi-doc/pull/171 Differential Revision: https://reviews.llvm.org/D95134	2021-01-22 07:55:24 +08:00
Craig Topper	704981b437	[RISCV] Update vmv.v.v-rv32.ll and vmv.v.v-rv64.ll to test the correct intrinsics. These were accidentally identical to the vmv.v.x tests. I must have fumbled when I copied them from our downstream repo.	2020-12-21 16:27:09 -08:00
Craig Topper	fc7b7fc066	[RISCV] Add intrinsics for vmv.v.v, vmv.v.x, and vmv.x.i We work with @rogfer01 from BSC to come out this patch. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Craig Topper <craig.topper@sifive.com> Differential Revision: https://reviews.llvm.org/D93514	2020-12-18 09:49:07 -08:00

Author

SHA1

Message

Date

Hsiangkai Wang

6e360460f1

[RISCV] Use v8-v23 as argument registers to conform to the proposal.

The maximum LMUL is 8. We need 16 vector registers for two LMUL-8
arguments. The modification follows the proposal of psABI in
https://github.com/riscv/riscv-elf-psabi-doc/pull/171

Differential Revision: https://reviews.llvm.org/D95134

2021-01-22 07:55:24 +08:00

Craig Topper

704981b437

[RISCV] Update vmv.v.v-rv32.ll and vmv.v.v-rv64.ll to test the correct intrinsics.

These were accidentally identical to the vmv.v.x tests. I must
have fumbled when I copied them from our downstream repo.

2020-12-21 16:27:09 -08:00

Craig Topper

fc7b7fc066

[RISCV] Add intrinsics for vmv.v.v, vmv.v.x, and vmv.x.i

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Craig Topper <craig.topper@sifive.com>

Differential Revision: https://reviews.llvm.org/D93514

2020-12-18 09:49:07 -08:00

3 Commits