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171853 Commits

Author SHA1 Message Date
Alp Toker 16f98b255d Fix some doc and comment typos 
llvm-svn: 205899
 2014-04-09 14:47:27 +00:00
Bradley Smith 246b0b617d [ARM64] Change SYS without a register to an alias to make disassembling more consistant. 
llvm-svn: 205898
 2014-04-09 14:44:58 +00:00
Bradley Smith 2cef19a2e6 [ARM64] Correctly disassemble ISB operand as ISB not DBarrier. 
llvm-svn: 205897
 2014-04-09 14:44:54 +00:00
Bradley Smith 239120cada [ARM64] Properly support both apple and standard syntax for FMOV 
llvm-svn: 205896
 2014-04-09 14:44:49 +00:00
Bradley Smith a2308f47d3 [ARM64] Flag setting logical/add/sub immediate instructions don't use SP. 
llvm-svn: 205895
 2014-04-09 14:44:44 +00:00
Bradley Smith f280e91849 [ARM64] Conditional branches must always print their condition code, even AL. 
llvm-svn: 205894
 2014-04-09 14:44:39 +00:00
Bradley Smith a19b7e83dc [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers. 
llvm-svn: 205893
 2014-04-09 14:44:36 +00:00
Bradley Smith a0d7a9a12f [ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional. 
llvm-svn: 205892
 2014-04-09 14:44:31 +00:00
Bradley Smith 70c6acbbfd [ARM64] Add missing shifted register MVN alias to ORN 
llvm-svn: 205891
 2014-04-09 14:44:26 +00:00
Bradley Smith 403bbf95c0 [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations. 
llvm-svn: 205890
 2014-04-09 14:44:22 +00:00
Bradley Smith 779238a216 [ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a dumb alias. 
llvm-svn: 205889
 2014-04-09 14:44:18 +00:00
Bradley Smith f823079acd [ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all labels types 
llvm-svn: 205888
 2014-04-09 14:44:12 +00:00
Bradley Smith af2710c96f [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions. 
llvm-svn: 205887
 2014-04-09 14:44:07 +00:00
Bradley Smith a0dce246ed [ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions. 
llvm-svn: 205886
 2014-04-09 14:44:03 +00:00
Bradley Smith 3971d3dc75 [ARM64] Rename LR to the UAL-compliant 'X30'. 
llvm-svn: 205885
 2014-04-09 14:43:59 +00:00
Bradley Smith 6f1aa59c31 [ARM64] Rename FP to the UAL-compliant 'X29'. 
llvm-svn: 205884
 2014-04-09 14:43:50 +00:00
Bradley Smith 5511f08055 [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be zero but should be decoded/disassembled with any value. 
llvm-svn: 205883
 2014-04-09 14:43:40 +00:00
Bradley Smith eb4ca04db2 [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0. 
llvm-svn: 205882
 2014-04-09 14:43:35 +00:00
Bradley Smith db7b9b17eb [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top bit of their immediate clear. 
llvm-svn: 205881
 2014-04-09 14:43:31 +00:00
Bradley Smith 60e7667886 [ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero. 
llvm-svn: 205880
 2014-04-09 14:43:27 +00:00
Bradley Smith 7525b47208 [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1. 
llvm-svn: 205879
 2014-04-09 14:43:24 +00:00
Bradley Smith 0243aa33fa [ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu. 
llvm-svn: 205878
 2014-04-09 14:43:20 +00:00
Bradley Smith 8f906a3c5f [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64. 
llvm-svn: 205877
 2014-04-09 14:43:15 +00:00
Bradley Smith 9f29b726d5 [ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases. 
llvm-svn: 205876
 2014-04-09 14:43:11 +00:00
Bradley Smith e8b4166acc [ARM64] Rework system register parsing to overcome SPSel clash in MSR variants. 
llvm-svn: 205875
 2014-04-09 14:43:06 +00:00
Bradley Smith bc35b1f138 [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value. 
llvm-svn: 205874
 2014-04-09 14:43:01 +00:00
Bradley Smith 4925be9b56 [ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disassembly. 
llvm-svn: 205873
 2014-04-09 14:42:56 +00:00
Bradley Smith 3339427e2a [ARM64] Remove PrefetchOp and use ARM64PRFM instead. 
llvm-svn: 205872
 2014-04-09 14:42:53 +00:00
Bradley Smith 16478c4ccf [ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway. 
llvm-svn: 205871
 2014-04-09 14:42:49 +00:00
Bradley Smith 3db2a85853 [ARM64] Remove ARM64SYS. 
llvm-svn: 205870
 2014-04-09 14:42:45 +00:00
Bradley Smith fb90df563f [ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS. 
llvm-svn: 205869
 2014-04-09 14:42:42 +00:00
Bradley Smith 08c391c156 [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process. 
llvm-svn: 205868
 2014-04-09 14:42:36 +00:00
Bradley Smith 2ba17a4a17 [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent. 
llvm-svn: 205867
 2014-04-09 14:42:27 +00:00
Bradley Smith ceeb04df60 [ARM64] Copy the named immediate operand mapping logic and enums from AArch64. AArch64's named immediate mapping and parsing is much more advanced than ARM64's. No functionality change - they're currently living side by side while I switch uses over. 
llvm-svn: 205866
 2014-04-09 14:42:16 +00:00
Bradley Smith 8c0b88c987 [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11. 
llvm-svn: 205865
 2014-04-09 14:42:11 +00:00
Bradley Smith 527bf86e56 [ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL) 
llvm-svn: 205864
 2014-04-09 14:42:07 +00:00
Bradley Smith 6d7af17a3f [ARM64] Add missing 1Q -> 1q vector kind alias 
llvm-svn: 205863
 2014-04-09 14:42:01 +00:00
Bradley Smith 7d253f29a4 [ARM64] Add parsing for vector lists such as {v0.8b-v3.8b} 
llvm-svn: 205862
 2014-04-09 14:41:58 +00:00
Bradley Smith 664aa67153 [ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather than UXTX 
llvm-svn: 205861
 2014-04-09 14:41:53 +00:00
Bradley Smith 35cadc58c9 [ARM64] STRHro and STRBro were not being decoded at all. 
llvm-svn: 205860
 2014-04-09 14:41:49 +00:00
Bradley Smith 87c60e00d5 [ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4. 
llvm-svn: 205859
 2014-04-09 14:41:45 +00:00
Bradley Smith cd91e5cd0c [ARM64] Register-offset loads and stores with the 'option' field equal to 00x or 10x are undefined. 
llvm-svn: 205858
 2014-04-09 14:41:38 +00:00
Filipe Cabecinhas 2c4e8ae0fd Revert "YAMLIO: Encode ambiguous hex strings explicitly" 
This reverts commit r205839.

It broke several tests in lld.

llvm-svn: 205857
 2014-04-09 14:35:17 +00:00
Arnold Schwaighofer fd0bf5d6e5 SLPVectorizer: Only vectorize intrinsics whose operands are widened equally 
The vectorizer only knows how to vectorize intrinics by widening all operands by
the same factor.

Patch by Tyler Nowicki!

llvm-svn: 205855
 2014-04-09 14:20:47 +00:00
Samuel Benzaquen 110f3cc45a Extend the check to detect patterns like 'ptr.get() == nullptr' 
Summary:
Extend the check to detect patterns like 'ptr.get() == nullptr'
It detects == and != when any argument is a ptr.get() and the other is a
nullptr.
Only supports standard smart pointer types std::unique_ptr and std::shared_ptr.
Does not support the case 'ptr.get() == other.get()' yet.

Reviewers: djasper

CC: cfe-commits, alexfh

Differential Revision: http://llvm-reviews.chandlerc.com/D3294

llvm-svn: 205854
 2014-04-09 14:17:23 +00:00
Daniel Jasper b55248278f clang-format: Update flag documentation, and generation script. 
llvm-svn: 205853
 2014-04-09 14:05:49 +00:00
Viktor Kutuzov 82185a2088 Declare _DYNAMIC and dl_phdr_info in asan_linux.cc on FreeBSD 
llvm-svn: 205852
 2014-04-09 13:37:19 +00:00
Daniel Jasper f9fc215f82 clang-format: Treat a trailing comment like a trailing comma in braced lists. 
Before:
  static StructInitInfo module = {MODULE_BUILTIN, /* type */
                                  "streams" /* name */
  };

After:
  static StructInitInfo module = {
      MODULE_BUILTIN, /* type */
      "streams"       /* name */
  };

This fixes llvm.org/PR19378.

llvm-svn: 205851
 2014-04-09 13:18:49 +00:00
Elena Demikhovsky cf0b9bafc3 AVX-512: insert element to mask vector; store i1 data 
Implemented INSERT_VECTOR_ELT operation for v16i1 and v8i1 vectors;
Implemented "store" for i1 type

llvm-svn: 205850
 2014-04-09 12:37:50 +00:00
Daniel Jasper 21397a3232 clang-format: Fix bug where clang-format would break the code. 
Before, it would turn:
  SomeFunction([]() { // Cool function..
    return 43;
  });

Into this:
  SomeFunction([]() { // Cool function.. return 43; });

llvm-svn: 205849
 2014-04-09 12:21:48 +00:00