Commit Graph

5 Commits

Author SHA1 Message Date
Simon Pilgrim 081abbb164 [X86][SSE] Improve lowering of vXi64 multiplies
As mentioned on PR30845, we were performing our vXi64 multiplication as:

AloBlo = pmuludq(a, b);
AloBhi = pmuludq(a, psrlqi(b, 32));
AhiBlo = pmuludq(psrlqi(a, 32), b);
return AloBlo + psllqi(AloBhi, 32)+ psllqi(AhiBlo, 32);

when we could avoid one of the upper shifts with:

AloBlo = pmuludq(a, b);
AloBhi = pmuludq(a, psrlqi(b, 32));
AhiBlo = pmuludq(psrlqi(a, 32), b);
return AloBlo + psllqi(AloBhi + AhiBlo, 32);

This matches the lowering on gcc/icc.

Differential Revision: https://reviews.llvm.org/D27756

llvm-svn: 290267
2016-12-21 20:00:10 +00:00
Simon Pilgrim 33f138b566 [X86][SSE] Added extra (mul x, (1 << c)) -> x << c style vector tests
vXi64 will benefit more from lowering to shifts than multiplies

llvm-svn: 284461
2016-10-18 09:29:13 +00:00
Simon Pilgrim cb59b5257c [DAGCombiner] Add vector support to (mul (shl X, Y), Z) -> (shl (mul X, Z), Y) style combines
llvm-svn: 284122
2016-10-13 14:04:35 +00:00
Simon Pilgrim 26b6dbc369 Copy+pasts typo in comment describing combine test
Repeated the "fold (mul x, 0) -> 0" instead of "fold (mul x, 1) -> x"

llvm-svn: 284118
2016-10-13 12:54:32 +00:00
Simon Pilgrim d4473f1126 [X86][SSE] Added vector mul combine tests
llvm-svn: 281839
2016-09-17 20:06:16 +00:00