5a4bcc749a
Use uint16_t to store instruction implicit uses and defs. Reduces static data.
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llvm-svn: 152301
2012-03-08 08:22:45 +00:00
d31658d44c
Re-commit r152202 hopefully fixing the MSVC linker error.
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Original commit message:
Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable.
llvm-svn: 152296
2012-03-08 06:55:27 +00:00
3048107bc1
Revert r152202 as it's causing internal buildbot failures.
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Original commit message:
Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect
all 16-bit string table offsets. Also make sure the string to offset table
string is not larger than 65536 characters since larger string literals aren't
portable.
llvm-svn: 152233
2012-03-07 17:06:40 +00:00
8d68422121
Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable.
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llvm-svn: 152202
2012-03-07 05:17:23 +00:00
ed428bc1ce
ARM more NEON VLD/VST composite physical register refactoring.
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Register pair, all lanes subscripting.
llvm-svn: 152157
2012-03-06 23:10:38 +00:00
13a292cc74
ARM refactor more NEON VLD/VST instructions to use composite physregs
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Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
llvm-svn: 152150
2012-03-06 22:01:44 +00:00
773642d3d8
Fix support for encodings up to 64-bits in length. TableGen was silently truncating them to 32-bits prior to this.
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llvm-svn: 152148
2012-03-06 21:48:32 +00:00
93d65c785e
Use uint16_t to store indices into string table since C++ only allows 64K string literals so the index into the big string can never be larger than that.
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llvm-svn: 152105
2012-03-06 06:04:39 +00:00
f875c10fda
Add asserts to ensure that values will fit into the tables.
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llvm-svn: 152104
2012-03-06 04:39:52 +00:00
6cbf0f13dd
Nuke a bit of dead code.
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llvm-svn: 152067
2012-03-05 23:09:51 +00:00
e5307f9019
ARM Refactor VLD/VST spaced pair instructions.
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Use the new composite physical registers.
llvm-svn: 152063
2012-03-05 21:43:40 +00:00
c988e0c521
ARM refactor away a bunch of VLD/VST pseudo instructions.
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With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.
llvm-svn: 152045
2012-03-05 19:33:30 +00:00
d3e7057afc
Shrink and reorder fields in MCRegisterClass to reduce size of static data.
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llvm-svn: 152019
2012-03-05 08:33:33 +00:00
4b02a29eba
Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.
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llvm-svn: 152016
2012-03-05 05:37:41 +00:00
1d32658877
Use uint16_t to store register overlaps to reduce static data.
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llvm-svn: 152001
2012-03-04 10:43:23 +00:00
b35eacb0f0
Use uint16_t instead of unsigned to store registers in reg classes. Reduces static data size.
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llvm-svn: 151998
2012-03-04 10:16:38 +00:00
420525ce3b
Use uint16_t to store registers in callee saved register tables to reduce size of static data.
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llvm-svn: 151996
2012-03-04 03:33:22 +00:00
6dedbae429
Use uint8_t instead of enums to store values in X86 disassembler table. Shaves 150k off the size of X86DisassemblerDecoder.o
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llvm-svn: 151995
2012-03-04 02:16:41 +00:00
0764a3fb72
Perform the string table optimization for OperandMatchEntries too.
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llvm-svn: 151986
2012-03-03 20:44:43 +00:00
5aeee5f854
Shrink the asm matcher tables.
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- Shrink the opcode field to 16 bits.
- Shrink the AsmVariantID field to 8 bits.
- Store the mnemonic string in a string table, store a 16 bit index.
- Store a pascal-style length byte in the string instead of a null terminator,
so we can avoid calling strlen on every entry we visit during mnemonic search.
Shrinks X86AsmParser.o from 434k to 201k on x86_64 and eliminates relocs from the table.
llvm-svn: 151984
2012-03-03 19:13:26 +00:00
dbe7f3bf2e
StringToOffsetTable: Allow uniquing the first element, add an option to skip appending a terminating null.
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llvm-svn: 151983
2012-03-03 19:13:20 +00:00
c3098f2ab2
Move getSubRegIndex out of generated code into MCRegisterInfo, devirtualize it.
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llvm-svn: 151821
2012-03-01 18:16:35 +00:00
e89025b8ce
Move TargetRegisterInfo::getSubReg() to MCRegisterInfo.
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Allows us to de-virtualize the function and provides access to it in
the instruction printer, which is useful for handling composite
physical registers (e.g., ARM register lists).
llvm-svn: 151815
2012-03-01 17:30:39 +00:00
53733cdb23
Revert "Emit the SubRegTable with the smallest possible integer type."
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This reverts commit 151760.
We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo,
but to do that, the type of the lookup table needs to be the same for
all targets.
llvm-svn: 151814
2012-03-01 17:30:35 +00:00
e39d7ac396
Make TargetRegisterClasses non-virtual by making the only virtual function a function pointer.
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This allows us to make TRC non-polymorphic and value-initializable, eliminating a huge static
initializer and a ton of cruft from the generated code.
Shrinks ARMBaseRegisterInfo.o by ~100k.
llvm-svn: 151806
2012-03-01 13:37:55 +00:00
acd78d5092
Emit the "is an intrinsic overloaded" table as a bitfield.
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llvm-svn: 151792
2012-03-01 02:16:57 +00:00
aba3503639
Emit the intrinsic modref info as a lookup table instead of a huge switch.
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Shrinks BasicAliasAnalysis.o from 106k to 56k on i386.
llvm-svn: 151781
2012-03-01 01:18:32 +00:00
0aafd06a85
Implement getSubRegIndex as a linear search on the SubRegTable instead of using a big switch.
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- The search bounds are constant, in the worst case (ARM target) it will scan over 30 uint16_ts.
- This method isn't very hot, I had problems finding a testcase where it's called more than a dozen of times (no perf impact).
llvm-svn: 151773
2012-02-29 23:46:50 +00:00
3f4b23933f
Tidy up. 80 columns.
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llvm-svn: 151764
2012-02-29 22:07:56 +00:00
c80c3fd5a7
Emit the SubRegTable with the smallest possible integer type.
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Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets.
llvm-svn: 151760
2012-02-29 21:57:08 +00:00
43bb61ea29
Tidy up. Spelling.
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llvm-svn: 151758
2012-02-29 21:46:32 +00:00
8d2f09117b
Move the subregister indicies enum into the REGINFO_ENUM section.
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llvm-svn: 151756
2012-02-29 21:43:16 +00:00
f591df6dd7
Switch TargetRegisterInfo::getSubReg() to use a lookup table.
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Instead of nested switch statements, use a lookup table. On ARM, this replaces
a 23k (x86_64 release build) function with a 16k table. Its not unlikely to
be faster, as well.
llvm-svn: 151751
2012-02-29 20:31:17 +00:00
ccd651cac8
Convert generated intrinsic attributes to use an array lookup as Chris suggested in PR11951.
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llvm-svn: 151622
2012-02-28 06:32:00 +00:00
8e76068c6e
Update tblgen command guide. Remove unused tblgen InstrEnumEmitter files.
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llvm-svn: 151513
2012-02-27 02:31:09 +00:00
6491c8020e
X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo.
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llvm-svn: 151510
2012-02-27 01:54:29 +00:00
243582995a
Remove 'if' from getSuperRegisters, getSubRegisters, and getOverlaps that were added in r151038.
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llvm-svn: 151246
2012-02-23 08:42:06 +00:00
cc830f8cda
Declare register classes as const. Fix a couple pointers to register classes that weren't already const.
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llvm-svn: 151138
2012-02-22 07:28:11 +00:00
760b134ffa
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
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llvm-svn: 151134
2012-02-22 05:59:10 +00:00
028a6721c9
Reorder some members in MCRegisterClass to remove padding on 64-bit builds.
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llvm-svn: 151043
2012-02-21 07:36:39 +00:00
da991549c0
In generated RegisterInfo files, replace a pointer to the end of an array with just the size of the array to avoid relocations.
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llvm-svn: 151041
2012-02-21 06:54:41 +00:00
9a511519e4
Merge some tables in generated RegisterInfo file. Store indices into larger table instead of pointers to reduce relocations and shrink table size on 64-bit builds. Shaves ~24K off X86MCTargetDesc.o. Accidentally commited only part of this in r151038.
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llvm-svn: 151039
2012-02-21 06:23:21 +00:00
636a3d618c
Remove dead code. Improve llvm_unreachable text. Simplify some control flow.
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llvm-svn: 150918
2012-02-19 11:37:01 +00:00
66a3597a4a
Add vmfunc instruction to X86 assembler and disassembler.
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llvm-svn: 150899
2012-02-19 01:39:49 +00:00
ed7aa46366
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
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llvm-svn: 150873
2012-02-18 08:19:49 +00:00
428704eb52
Make the EDis tables const.
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llvm-svn: 150304
2012-02-11 14:51:07 +00:00
478e8de8ef
Reuse the enum names from X86Desc in the X86Disassembler.
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This requires some gymnastics to make it available for C code. Remove the names
from the disassembler tables, making them relocation free.
llvm-svn: 150303
2012-02-11 14:50:54 +00:00
bf152d57a4
Put instruction names into an indexed string table on the side, removing a pointer from MCInstrDesc.
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Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't
have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64.
llvm-svn: 150245
2012-02-10 13:18:44 +00:00
c602b6ecaf
Store just the SimpleValueType in the generated VT tables for each register class, eliminating static ctors.
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llvm-svn: 150173
2012-02-09 12:35:37 +00:00
8e012f5f22
Move the Name field in MCInstrDesc to the end, saving 8 bytes of padding per entry on x86_64.
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No change on i386.
llvm-svn: 150170
2012-02-09 11:25:09 +00:00
Craig Topper