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41 Commits

Author SHA1 Message Date
Nate Begeman 2fba8a3aaa bswap implementation 
llvm-svn: 25312
 2006-01-14 03:14:10 +00:00
Evan Cheng dba84bbc1e LHS = X86ISD::CMOVcc LHS, RHS means LHS = RHS if cc. So the operands must be 
flipped around.

llvm-svn: 25290
 2006-01-13 19:51:46 +00:00
Chris Lattner 1a8d918ef1 Enable X86 support for savestack/restorestack 
llvm-svn: 25278
 2006-01-13 18:00:54 +00:00
Chris Lattner 8e2f52e645 expand unsupported stacksave/stackrestore nodes 
llvm-svn: 25272
 2006-01-13 02:42:53 +00:00
Evan Cheng d7faa4bae1 More typo's. I need new eye glasses... 
llvm-svn: 25261
 2006-01-13 01:17:24 +00:00
Evan Cheng 731423f36a Oops. Typo. 
llvm-svn: 25260
 2006-01-13 01:06:49 +00:00
Evan Cheng fb22e86c4d Fix a SETCC / BRCOND folding bug. 
llvm-svn: 25259
 2006-01-13 01:03:02 +00:00
Evan Cheng 6305e50ee1 Fix sint_to_fp (fild*) support. 
llvm-svn: 25257
 2006-01-12 22:54:21 +00:00
Evan Cheng 84dc9b55f0 X86ISD::SETCC (e.g. SETEr) produces a flag (so multiple SETCC can be 
linked together).

llvm-svn: 25247
 2006-01-12 08:27:59 +00:00
Evan Cheng b94db9e9a4 * Materialize GlobalAddress and ExternalSym with MOV32ri rather than 
LEA32r.
* Do not lower GlobalAddress to TargetGlobalAddress. Let isel does it.

llvm-svn: 25246
 2006-01-12 07:56:47 +00:00
Evan Cheng 6d2ab04463 Added ROTL and ROTR. 
llvm-svn: 25232
 2006-01-11 23:20:05 +00:00
Evan Cheng ae986f1f1e Support for MEMCPY and MEMSET. 
llvm-svn: 25226
 2006-01-11 22:15:48 +00:00
Nate Begeman 1b8121b227 Add bswap, rotl, and rotr nodes 
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl

Targets should add rotl/rotr patterns if they have them

llvm-svn: 25222
 2006-01-11 21:21:00 +00:00
Evan Cheng bc7a0f44bd * Add special entry code main() (to set x87 to 64-bit precision). 
* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
  call parmater passing.

llvm-svn: 25207
 2006-01-11 06:09:51 +00:00
Evan Cheng 339edad775 SSE cmov support. 
llvm-svn: 25190
 2006-01-11 00:33:36 +00:00
Evan Cheng 73a1ad975e FP_TO_INT*_IN_MEM and x87 FP Select support. 
llvm-svn: 25188
 2006-01-10 20:26:56 +00:00
Evan Cheng 12181af0c7 More typos 
llvm-svn: 25162
 2006-01-09 22:29:54 +00:00
Evan Cheng 77fa9195cd typo 
llvm-svn: 25160
 2006-01-09 20:49:21 +00:00
Evan Cheng 9c249c37f8 Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. 
llvm-svn: 25158
 2006-01-09 18:33:28 +00:00
Evan Cheng 172fce7050 * Fast call support. 
* FP cmp, setcc, etc.

llvm-svn: 25117
 2006-01-06 00:43:03 +00:00
Jim Laskey deeafa0f00 Had expand logic backward. 
llvm-svn: 25105
 2006-01-05 01:47:43 +00:00
Jim Laskey 762e9ec06c Added initial support for DEBUG_LABEL allowing debug specific labels to be 
inserted in the code.

llvm-svn: 25104
 2006-01-05 01:25:28 +00:00
Evan Cheng 45e19098a6 DAG based isel call support. 
llvm-svn: 25103
 2006-01-05 00:27:02 +00:00
Chris Lattner 8258489ca4 Fix a problem duraid pointed out to me compiling kc++ with -enable-x86-fastcc 
llvm-svn: 25024
 2005-12-27 03:02:18 +00:00
Evan Cheng 5c59d49630 More X86 floating point patterns. 
llvm-svn: 24990
 2005-12-23 07:31:11 +00:00
Chris Lattner 30107e65c8 make sure bit_convert's are expanded 
llvm-svn: 24979
 2005-12-23 05:15:23 +00:00
Evan Cheng 9cdc16c6d3 * Fix a GlobalAddress lowering bug. 
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.

llvm-svn: 24921
 2005-12-21 23:05:39 +00:00
Jim Laskey 9e296bee9a Disengage DEBUG_LOC from non-PPC targets. 
llvm-svn: 24919
 2005-12-21 20:51:37 +00:00
Evan Cheng c1583dbd63 * Added support for X86 RET with an additional operand to specify number of 
bytes to pop off stack.
* Added support for X86 SETCC.

llvm-svn: 24917
 2005-12-21 20:21:51 +00:00
Evan Cheng a74ce62746 * Added lowering hook for external weak global address. It inserts a load 
for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
  value (or store / fld / copy to ST(0) for floating point value). This
  eliminate the need to write C++ code to handle RET with variable number
  of operands.

llvm-svn: 24888
 2005-12-21 02:39:21 +00:00
Evan Cheng 6af02635a7 Added a hook to print out names of target specific DAG nodes. 
llvm-svn: 24877
 2005-12-20 06:22:03 +00:00
Evan Cheng 6fc31046aa X86 conditional branch support. 
llvm-svn: 24870
 2005-12-19 23:12:38 +00:00
Evan Cheng f3b16bc5a0 Remove a few lines of dead code. 
llvm-svn: 24768
 2005-12-17 07:18:44 +00:00
Evan Cheng 225a4d0d6d X86 lowers SELECT to a cmp / test followed by a conditional move. 
llvm-svn: 24754
 2005-12-17 01:21:05 +00:00
Evan Cheng 74151ba279 * Promote all 1 bit entities to 8 bit. 
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.

llvm-svn: 24726
 2005-12-15 19:49:23 +00:00
Chris Lattner 3225733e65 X86 doesn't support sextinreg for 8-bit things either. 
llvm-svn: 24631
 2005-12-07 17:59:14 +00:00
Chris Lattner 9c415364cf No targets support line number info yet. 
llvm-svn: 24513
 2005-11-29 06:16:21 +00:00
Chris Lattner 6c1ca888d4 Lower READCYCLECOUNTER correctly, preserving the chain result 
llvm-svn: 24438
 2005-11-20 22:57:19 +00:00
Chris Lattner 6df9e11989 use chain operands to ensure the copies don't wander from the rdtsc instruction. 
llvm-svn: 24434
 2005-11-20 22:01:40 +00:00
Andrew Lenharth 0bf68ae434 The second patch of X86 support for read cycle counter. 
llvm-svn: 24430
 2005-11-20 21:41:10 +00:00
Chris Lattner 76ac068568 Separate X86ISelLowering stuff out from the X86ISelPattern.cpp file. Patch 
contributed by Evan Cheng.

llvm-svn: 24358
 2005-11-15 00:40:23 +00:00