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24457 Commits

Author SHA1 Message Date
Arnold Schwaighofer e937592ef2 ARMInstrInfo: Improve isSwiftFastImmShift 
An instruction with less than 3 inputs is trivially a fast immediate shift.

Reapply of 183256, should not have caused the tablegen segfault on linux either.

llvm-svn: 183314
 2013-06-05 14:59:36 +00:00
Mihai Popa 0e9892fe3a This is a simple patch that changes RRX and RRXS to accept all registers as operands. 
According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp.

llvm-svn: 183307
 2013-06-05 13:23:51 +00:00
Tom Stellard aad5376fb6 R600: Make sure to schedule AR register uses and defs in the same clause 
Reviewed-by: vljn at ovi.com
llvm-svn: 183294
 2013-06-05 03:43:06 +00:00
Rafael Espindola beef23fe21 Revert "R600: Add a pass that merge Vector Register" 
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.

llvm-svn: 183286
 2013-06-05 01:48:30 +00:00
Rafael Espindola 806f006490 Handle relocations that don't point to symbols. 
In ELF (as in MachO), not all relocations point to symbols. Represent this
properly by using a symbol_iterator instead of a SymbolRef. Update llvm-readobj
ELF's dumper to handle relocatios without symbols.

llvm-svn: 183284
 2013-06-05 01:33:53 +00:00
Vincent Lejeune a45aafabfe R600: Add a pass that merge Vector Register 
llvm-svn: 183279
 2013-06-04 23:17:26 +00:00
Vincent Lejeune c689679173 R600: Const/Neg/Abs can be folded to dot4 
llvm-svn: 183278
 2013-06-04 23:17:15 +00:00
Evan Cheng 4ec309700b Cortex-R5 can issue Thumb2 integer division instructions. 
llvm-svn: 183275
 2013-06-04 22:52:09 +00:00
Arnold Schwaighofer 2a70c69d31 Revert series of sched model patches until I figure out what is going on. 
llvm-svn: 183273
 2013-06-04 22:35:17 +00:00
Arnold Schwaighofer 0024b8bd73 ARM sched model: Add VFP div instruction on Swift 
llvm-svn: 183271
 2013-06-04 22:16:08 +00:00
Arnold Schwaighofer 89901730b1 ARM sched model: Add SIMD/VFP load/store instructions on Swift 
llvm-svn: 183270
 2013-06-04 22:16:07 +00:00
Arnold Schwaighofer bc61f0912c ARM sched model: Add integer VFP/SIMD instructions on Swift 
llvm-svn: 183269
 2013-06-04 22:16:05 +00:00
Arnold Schwaighofer 83a4197085 ARM sched model: Add integer load/store instructions on Swift 
llvm-svn: 183268
 2013-06-04 22:16:04 +00:00
Arnold Schwaighofer f77ea45488 ARM sched model: Add integer arithmetic instructions on Swift 
llvm-svn: 183267
 2013-06-04 22:16:02 +00:00
Arnold Schwaighofer be3a06c85f ARM sched model: Cortex A9 - More InstRW sched resources 
Add more InstRW mappings.

llvm-svn: 183266
 2013-06-04 22:16:00 +00:00
Arnold Schwaighofer 76e2394799 ARM sched model: Add branch thumb instructions 
llvm-svn: 183265
 2013-06-04 22:15:59 +00:00
Arnold Schwaighofer 17359d9ba2 ARM sched model: Add branch thumb2 instructions 
llvm-svn: 183264
 2013-06-04 22:15:57 +00:00
Arnold Schwaighofer bdb5687468 ARM sched model: Add branch instructions 
llvm-svn: 183263
 2013-06-04 22:15:56 +00:00
Arnold Schwaighofer e971b08765 ARM sched model: Add preload thumb2 instructions 
llvm-svn: 183262
 2013-06-04 22:15:54 +00:00
Arnold Schwaighofer ab88312f51 ARM sched model: Add preload instructions 
llvm-svn: 183261
 2013-06-04 22:15:52 +00:00
Arnold Schwaighofer 83fa45629e ARM sched model: Add more ALU and CMP thumb instructions 
llvm-svn: 183260
 2013-06-04 22:15:51 +00:00
Arnold Schwaighofer 529c2be334 ARM sched model: Add more ALU and CMP thumb2 instructions 
llvm-svn: 183259
 2013-06-04 22:15:49 +00:00
Arnold Schwaighofer b6843f17eb ARM sched model: Add more ALU and CMP instructions 
llvm-svn: 183258
 2013-06-04 22:15:47 +00:00
Arnold Schwaighofer d5b9794a53 ARM sched model: Add divsion, loads, branches, vfp cvt 
Add some generic SchedWrites and assign resources for Swift and Cortex A9.

llvm-svn: 183257
 2013-06-04 22:15:46 +00:00
Arnold Schwaighofer 279c0aff1a ARMInstrInfo: Improve isSwiftFastImmShift 
An instruction with less than 3 inputs is trivially a fast immediate shift.

llvm-svn: 183256
 2013-06-04 22:15:43 +00:00
Venkatraman Govindaraju a54533ed78 Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 
llvm-svn: 183243
 2013-06-04 18:33:25 +00:00
David Majnemer 452f1f97bd ARM: Fix crash in ARM backend inside of ARMConstantIslandPass 
The ARM backend did not expect LDRBi12 to hold a constant pool operand.
Allow for LLVM to deal with the instruction similar to how it deals with
LDRi12.

This fixes PR16215.

llvm-svn: 183238
 2013-06-04 17:46:15 +00:00
Vincent Lejeune 276ceb8d5f R600: Swizzle texture/export instructions 
llvm-svn: 183229
 2013-06-04 15:04:53 +00:00
Vladimir Medic ea381916b0 Test commit for user vmedic, to verify commit access. One line of comment is added to MipsAsmParser.cpp. 
llvm-svn: 183215
 2013-06-04 08:28:53 +00:00
Aaron Ballman 19978553d4 Silencing an MSVC warning about mixing bool and unsigned int. 
llvm-svn: 183176
 2013-06-04 01:03:03 +00:00
Tom Stellard 94593ee8c3 R600/SI: Add support for work item and work group intrinsics 
llvm-svn: 183138
 2013-06-03 17:40:18 +00:00
Tom Stellard ed882c2f1b R600/SI: Add a calling convention for compute shaders 
llvm-svn: 183137
 2013-06-03 17:40:11 +00:00
Tom Stellard 046039e81b R600/SI: Custom lower i64 sign_extend 
llvm-svn: 183136
 2013-06-03 17:40:03 +00:00
Tom Stellard 0518ff89ba R600/SI: Adjust some instructions' out register class after ISel 
This is necessary to avoid generating VGPR to SGPR copies in some
cases.

llvm-svn: 183135
 2013-06-03 17:39:58 +00:00
Tom Stellard bad1f59212 R600/SI: Handle REG_SEQUENCE in fitsRegClass() 
llvm-svn: 183134
 2013-06-03 17:39:54 +00:00
Tom Stellard b5a97004fb R600/SI: Handle nodes with glue results correctly SITargetLowering::foldOperands() 
llvm-svn: 183133
 2013-06-03 17:39:50 +00:00
Tom Stellard 2183b70523 R600/SI: Fixup CopyToReg register class in PostprocessISelDAG() 
The CopyToReg nodes will sometimes try to copy a value from a VGPR to an
SGPR.  This kind of copy is not possible, so we need to detect
VGPR->SGPR copies and do something else.  The current strategy is to
replace these copies with VGPR->VGPR copies and hope that all the users
of CopyToReg can accept VGPRs as arguments.

llvm-svn: 183132
 2013-06-03 17:39:46 +00:00
Tom Stellard 07a10a3d3f R600/SI: Add support for global loads 
llvm-svn: 183131
 2013-06-03 17:39:43 +00:00
Tom Stellard 556d9aa841 R600/SI: Rework MUBUF store instructions 
The lowering of stores is now mostly handled in the tablegen files.  No
more BUFFER_STORE nodes I generated during legalization.

llvm-svn: 183130
 2013-06-03 17:39:37 +00:00
Vincent Lejeune 91a942b93e R600: 3 op instructions have no write bit but the result are store in PV 
llvm-svn: 183111
 2013-06-03 15:56:12 +00:00
Vincent Lejeune eabf83e0a2 R600: CALL_FS consumes a stack size entry 
llvm-svn: 183108
 2013-06-03 15:44:42 +00:00
Vincent Lejeune f83df1f1cb R600: use capital letter for PV channel 
llvm-svn: 183107
 2013-06-03 15:44:35 +00:00
Vincent Lejeune a09873dda7 R600: Constraints input regs of interp_xy,_zw 
llvm-svn: 183106
 2013-06-03 15:44:16 +00:00
Ahmed Bougacha 05d53a018a X86: sub_xmm registers are 128 bits wide. 
llvm-svn: 183103
 2013-06-03 14:42:40 +00:00
Venkatraman Govindaraju f80d72f149 Sparc: Add support for indirect branch and blockaddress in Sparc backend. 
llvm-svn: 183094
 2013-06-03 05:58:33 +00:00
Venkatraman Govindaraju 774fe2e29a Sparc: When storing 0, use %g0 directly in the store instruction instead of 
using two instructions (sethi and store).

llvm-svn: 183090
 2013-06-03 00:21:54 +00:00
Venkatraman Govindaraju 0bbe1b210e Sparc: Combine add/or/sethi instruction with restore if possible. 
llvm-svn: 183088
 2013-06-02 21:48:17 +00:00
Venkatraman Govindaraju 3e8c7d98be Sparc: Perform leaf procedure optimization by default 
llvm-svn: 183083
 2013-06-02 02:24:27 +00:00
Venkatraman Govindaraju 28e2cd0e7e Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics as non-leaf functions. 
llvm-svn: 183079
 2013-06-01 20:42:48 +00:00
Tim Northover 339bf154cc Revert r183069: "TMP: LEA64_32r fixing" 
Very sorry, it was committed from the wrong branch by mistake.

llvm-svn: 183070
 2013-06-01 10:23:46 +00:00