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Author SHA1 Message Date
Stanislav Mekhanoshin 443a7f9788 [AMDGPU] Disable DAG combine at -O0 
Differential Revision: https://reviews.llvm.org/D54358

llvm-svn: 347659
 2018-11-27 15:13:37 +00:00
Alexander Timofeev db7ee7660a [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed 
Differential revision: https://reviews.llvm.org/D51734
Reviewers: rampitec

llvm-svn: 341928
 2018-09-11 11:56:50 +00:00
Stanislav Mekhanoshin 3b11794dbf [AMDGPU] setcc (select cc, CT, CF), CF, eq | ne -> xor cc, -1 | cc 
This is the common case in the BE when we serialize condition and then
rematerialize it. Use either original or inverted condition.

Differential Revision: https://reviews.llvm.org/D48246

llvm-svn: 334882
 2018-06-16 03:46:59 +00:00