Commit Graph

274041 Commits

Author SHA1 Message Date
whitequark ae12efab20 [MergeFunctions] Merge small functions if possible without a thunk.
This can result in significant code size savings in some cases,
e.g. an interrupt table all filled with the same assembly stub
in a certain Cortex-M BSP results in code blowup by a factor of 2.5.

Differential Revision: https://reviews.llvm.org/D34806

llvm-svn: 315853
2017-10-15 12:29:09 +00:00
whitequark b2ce9ffede [MergeFunctions] Replace all uses of unnamed_addr functions.
This reduces code size for constructs like vtables or interrupt
tables that refer to functions in global initializers.

Differential Revision: https://reviews.llvm.org/D34805

llvm-svn: 315852
2017-10-15 12:29:01 +00:00
Amjad Aboud c8d67979c0 [X86] Ignore DBG instructions in X86CmovConversion optimization to resolve PR34565
Differential Revision: https://reviews.llvm.org/D38359

llvm-svn: 315851
2017-10-15 11:00:56 +00:00
Hongbin Zheng 73f650435b [LoopInfo][Refactor] Make SetLoopAlreadyUnrolled a member function of the Loop Pass, NFC.
This avoid code duplication and allow us to add the disable unroll metadata elsewhere.

Differential Revision: https://reviews.llvm.org/D38928

llvm-svn: 315850
2017-10-15 07:31:02 +00:00
Craig Topper a9cd59fb5d [X86] Lower vselect with constant condition to vector_shuffle even with AVX512 instructions.
Summary:
It's better to use our shuffle lowering code to handle these than loading an immediate into a k-register.

It really feels like this should be a DAG combine optimization rather than a lowering operation, but that's a problem for another day.

Reviewers: RKSimon, delena, zvi

Reviewed By: delena

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38932

llvm-svn: 315849
2017-10-15 06:39:07 +00:00
Craig Topper f02e97859b [X86] Don't use constant condition for select instruction when testing masking ops.
We should be able to fold constant conditions by converting to shuffles, but fixing that would break these tests in their current form. Since they are really trying to test masking ops, add a non-constant mask to the selects.

llvm-svn: 315848
2017-10-15 06:05:50 +00:00
Vitaly Buka 7450398e01 Remove unused variables
llvm-svn: 315847
2017-10-15 05:35:02 +00:00
Benjamin Kramer 8b54a1c686 [Lex] Remove unused variables. No functionality change.
llvm-svn: 315845
2017-10-15 04:27:37 +00:00
Vitaly Buka ac03fb616f [asan] Increase kHandlerStackSize for TracerThreadSignalHandler
4096 is not enough on some platform, e.g. Debian 4.9.0-3-amd64

llvm-svn: 315844
2017-10-15 04:18:29 +00:00
Daniel Sanders 39690bdf42 [globalisel][tablegen] Map ld and st to G_LOAD and G_STORE. NFC
Summary:
There is an important mismatch between ISD::LOAD and G_LOAD (and likewise for
ISD::STORE and G_STORE). In SelectionDAG, ISD::LOAD is a non-atomic load
and atomic loads are handled by a separate node. However, this is not true of
GlobalISel's G_LOAD. For G_LOAD, the MachineMemOperand indicates the atomicity
of the operation. As a result, this mapping must also add a predicate that
checks for non-atomic MachineMemOperands.

This is NFC since these nodes always have predicates in practice and are
therefore always rejected at the moment.

Depends on D37443

Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar

Reviewed By: qcolombet

Subscribers: kristof.beyls, llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D37445

llvm-svn: 315843
2017-10-15 02:41:12 +00:00
Faisal Vali b7c0b089f2 [c++2a] Fix failing regression test related to not adding the extension warning to a diagnostic group (in r315840)
In passing also complete a comment that I left uncompleted.

For ease of reference, here's the parent commit: https://reviews.llvm.org/rL315840

llvm-svn: 315842
2017-10-15 02:13:17 +00:00
Daniel Sanders 3f267bf769 [tablegen] Handle common load/store predicates inside tablegen. NFC.
Summary:
GlobalISel and SelectionDAG require different code for the common
load/store predicates due to differences in the representation.
For example:
   SelectionDAG: (load<signext,i8>:i32 GPR32:$addr) // The <> denote properties of the SDNode that are not printed in the DAG
   GlobalISel: (G_SEXT:s32 (G_LOAD:s8 GPR32:$addr))
Even without that, differences in the IR (SDNode vs MachineInstr) require
differences in the C++ predicate.

This patch moves the implementation of the common load/store predicates
into tablegen so that it can handle these differences.

It's NFC for SelectionDAG since it emits equivalent code and it's NFC for
GlobalISel since the rules involving the relevant predicates are still
rejected by the importer.

Depends on D36618

Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar

Subscribers: llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D37443

Includes a partial revert of r315826 since this patch makes it necessary for
getPredCode() to return a std::string and getImmCode() should have the same
interface as getPredCode().

llvm-svn: 315841
2017-10-15 02:06:44 +00:00
Faisal Vali 1826842865 [c++2a] Implement P0306 __VA_OPT__ (Comma omission and comma deletion)
This patch implements an extension to the preprocessor:

__VA_OPT__(contents) --> which expands into its contents if variadic arguments are supplied to the parent macro, or behaves as an empty token if none.

  - Currently this feature is only enabled for C++2a (this could be enabled, with some careful tweaks, for other dialects with the appropriate extension or compatibility warnings)

  - The patch was reviewed here: https://reviews.llvm.org/D35782 and asides from the above (and moving some of the definition and expansion recognition logic into the corresponding state machines), I believe I incorporated all of Richard's suggestions.

A few technicalities (most of which were clarified through private correspondence between rsmith, hubert and thomas) are worth mentioning.  Given:

    #define F(a,...) a #__VA_OPT__(a ## a)  a ## __VA_OPT__(__VA_ARGS__)

    - The call F(,) Does not supply any tokens for the variadic arguments and hence VA_OPT behaves as a placeholder.
    - When expanding VA_OPT (for e.g. F(,1) token pasting occurs eagerly within its contents if the contents need to be stringified.
    - A hash or a hashhash prior to VA_OPT does not inhibit expansion of arguments if they are the first token within VA_OPT.
    - When a variadic argument is supplied, argument substitution occurs within the contents as does stringification - and these resulting tokens are inserted back into the macro expansions token stream just prior to the entire stream being rescanned and concatenated.

See wg21.link/P0306 for further details on the feature.


Acknowledgment: This patch would have been poorer if not for Richard Smith's usual thoughtful analysis and feedback.
llvm-svn: 315840
2017-10-15 01:26:26 +00:00
Davide Italiano 76067588dc [Hexagon] Mark RangeTree::dump() with LLVM_DUMP_METHOD.
GCC otherwise emits a "defined but not used" warning on the
member function.

llvm-svn: 315838
2017-10-14 23:46:01 +00:00
Konstantin Zhuravlyov 263f7f6676 AMDGPU: Temporary disable pal metadata check line in llvm-readobj test
It fails on mips

llvm-svn: 315837
2017-10-14 23:42:11 +00:00
Konstantin Zhuravlyov 202c1b715f Revert "Mark test as unsupported until r315808 is fixed"
Test is fixed in r315830

llvm-svn: 315831
2017-10-14 22:24:31 +00:00
Konstantin Zhuravlyov 8c18f5b3d4 AMDGPU: Don't use TargetStreamer if it has not been initialized
Fixes cfe/trunk/test/Misc/backend-resource-limit-diagnostics.cl
test after r315808

We may hit few other similar issues, but I want to discuss good
solution offline.

llvm-svn: 315830
2017-10-14 22:16:26 +00:00
Bruno Cardoso Lopes b37d05c9c1 Mark test as unsupported until r315808 is fixed
This is causing:
http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental/43381

llvm-svn: 315829
2017-10-14 22:14:23 +00:00
Craig Topper dfb443e88c [X86] Remove a bunch of dead FileCheck lines with the wrong prefix.
llvm-svn: 315828
2017-10-14 21:46:55 +00:00
George Karpenkov 1b11460610 [xray] Fix CMake for X-RAY tests
Correctly depend on llvm-xray, make sure unit tests are being run.

Differential Revision: https://reviews.llvm.org/D38917

llvm-svn: 315827
2017-10-14 21:38:13 +00:00
Simon Pilgrim 6ecae9fc97 [TableGen] Avoid unnecessary std::string creations
Avoid unnecessary std::string creations in the TreePredicateFn getters.

llvm-svn: 315826
2017-10-14 21:27:53 +00:00
Simon Pilgrim 36fe00ee17 [X86][SSE] Don't attempt to reduce the imul vector width of odd sized vectors (PR34947)
llvm-svn: 315825
2017-10-14 19:57:19 +00:00
Simon Pilgrim 3f49b988e0 [X86][SSE] Test vector imul reduction on 32 and 64-bit targets
llvm-svn: 315824
2017-10-14 19:46:08 +00:00
Bruno Cardoso Lopes caac2fbd19 Revert "[AArch64][RegisterBankInfo] Use the statically computed mappings for COPY"
This reverts commit r315781, breaks:
http://green.lab.llvm.org/green/job/Compiler_Verifiers_GlobalISEL/9882

llvm-svn: 315823
2017-10-14 19:31:03 +00:00
Konstantin Zhuravlyov 13376a4bdf AMDGPU: Add AMDGPU HSA Kernel Descriptor
- Update docs to match llvm coding style
  - Add missing FP16_OVFL bit for gfx9
  - Fix the size of the kernel descriptor in the docs

Differential Revision: https://reviews.llvm.org/D38902

llvm-svn: 315822
2017-10-14 19:17:08 +00:00
Konstantin Zhuravlyov a01d8b0b63 AMDGPU: Bring HSA metadata on par with the specification
Differential Revision: https://reviews.llvm.org/D38753

llvm-svn: 315821
2017-10-14 19:03:51 +00:00
Konstantin Zhuravlyov b3c605d680 llvm-readobj: Print AMDGPU note contents
Differential Revision: https://reviews.llvm.org/D38752

llvm-svn: 315819
2017-10-14 18:21:42 +00:00
Simon Pilgrim f5b9f353c3 Pull out repeated calls to VT.getVectorNumElements(). NFCI.
llvm-svn: 315818
2017-10-14 17:37:42 +00:00
Simon Pilgrim 5bd4431aec Cleanup update_llc_test_checks.py notes.
llvm-svn: 315817
2017-10-14 17:37:03 +00:00
Konstantin Zhuravlyov 7b4be1ed89 AMDGPU: Cleanup elf-notes.ll test
llvm-svn: 315816
2017-10-14 17:36:53 +00:00
Simon Pilgrim cded82837d Use DAG::getBitcast() helper. NFCI.
llvm-svn: 315815
2017-10-14 17:14:42 +00:00
Ed Maste 48652257bb libunwind: document tested FreeBSD configs and sort OS list
libunwind is known to work on FreeBSD i386, amd64 (x86_64) and arm64.
It is the unwinder provided by the base system on all of those
architectures.

While here sort the OS list.

Differential Revision:	https://reviews.llvm.org/D38900

llvm-svn: 315814
2017-10-14 17:04:04 +00:00
Konstantin Zhuravlyov 716af741e9 llvm-readobj: Print AMDGPU note type names
Differential Revision: https://reviews.llvm.org/D38751

llvm-svn: 315813
2017-10-14 16:43:46 +00:00
Konstantin Zhuravlyov 219066bab8 AMDGPU: Improve note directive verification in assembler
- Do not allow amd_amdgpu_isa directives on non-amdgcn architectures
  - Do not allow amd_amdgpu_hsa_metadata on non-amdhsa OSes
  - Do not allow amd_amdgpu_pal_metadata on non-amdpal OSes

Differential Revision: https://reviews.llvm.org/D38750

llvm-svn: 315812
2017-10-14 16:15:28 +00:00
Benjamin Kramer 2b8ad7312d Re-land r315787, "[Sema] Warn about unused variables if we can constant evaluate the initializer."
The warnings in libc++ tests were fixed in the meantime.

llvm-svn: 315811
2017-10-14 15:59:34 +00:00
Konstantin Zhuravlyov eda425edd4 AMDGPU: Do not emit deprecated notes for code object v3
Differential Revision: https://reviews.llvm.org/D38749

llvm-svn: 315810
2017-10-14 15:59:07 +00:00
Benjamin Kramer 346bd6a208 Placate unused variable warnings uncovered by improvements to clang's -Wunused-variable
llvm-svn: 315809
2017-10-14 15:52:38 +00:00
Konstantin Zhuravlyov 9c05b2bc3b AMDGPU: Add support for isa version note
- Emit NT_AMD_AMDGPU_ISA
  - Add assembler parsing for isa version directive
    - If isa version directive does not match command line arguments, then return error

Differential Revision: https://reviews.llvm.org/D38748

llvm-svn: 315808
2017-10-14 15:40:33 +00:00
Simon Pilgrim f367c27d2d [X86][SSE] Support combining AND(EXTRACT(SHUF(X)), C) -> EXTRACT(SHUF(X))
If we are applying a byte mask to a value extracted from a shuffle, see if we can combine the mask into shuffle.

Fixes the last issue with PR22415

llvm-svn: 315807
2017-10-14 15:01:36 +00:00
NAKAMURA Takumi 93638b751a Revert rL315787, "[Sema] Warn about unused variables if we can constant evaluate the initializer."
check-libcxx dislikes it.

llvm-svn: 315806
2017-10-14 14:46:04 +00:00
Yaxun Liu 98f0c43f85 Fix build failure on android due to missing std::to_string()
llvm-svn: 315805
2017-10-14 12:51:52 +00:00
Yaxun Liu c2a87a05f1 [OpenCL] Emit enqueued block as kernel
In OpenCL the kernel function and non-kernel function has different calling conventions.
For certain targets they have different argument ABIs. Also kernels have special function
attributes and metadata for runtime to launch them.

The blocks passed to enqueue_kernel is supposed to be executed as kernels. As such,
the block invoke function should be emitted as kernel with proper calling convention and
argument ABI.

This patch emits enqueued block as kernel. If a block is both called directly and passed
to enqueue_kernel, separate functions will be generated.

Differential Revision: https://reviews.llvm.org/D38134

llvm-svn: 315804
2017-10-14 12:23:50 +00:00
NAKAMURA Takumi 09c234f857 Revert rL315721, "Handle shared and lazy symbol in the gnu hash construction."
It broke check-libcxx with stage1-clang and stage1-lld.

llvm-svn: 315803
2017-10-14 12:21:49 +00:00
Craig Topper f7e777763d [X86] Add patterns for vzmovl+cvtpd2dq/cvttpd2dq with a load.
llvm-svn: 315802
2017-10-14 07:04:48 +00:00
Craig Topper 61010a85b8 [X86] Add AVX512 versions of VCVTPD2PS to load folding tables.
llvm-svn: 315801
2017-10-14 05:55:43 +00:00
Craig Topper ee277e190c [X86] Add patterns for vzmovl+cvtpd2ps with a load.
llvm-svn: 315800
2017-10-14 05:55:42 +00:00
Craig Topper aec05a9303 [X86] Remove some patterns for bitcasted alignednonedtemporalloads.
These select the same instruction as the non-bitcasted pattern. So this provides no additional value.

llvm-svn: 315799
2017-10-14 04:18:11 +00:00
Craig Topper 009f0aaeb0 [X86] Remove unnecessary bitconverts as the root of patterns for zero extended VCVTPD2UDQZ128rr and VCVTTPD2UDQZ128rr.
We don't need a bitconvert as a root pattern in these cases. The types in the other parts of the pattern are sufficient to express the behavior of these instructions.

llvm-svn: 315798
2017-10-14 04:18:10 +00:00
Craig Topper d746747d03 [X86] Add additional patterns for folding loads with 128-bit VCVTDQ2PD and VCVTUDQ2PD.
This matches the patterns we have for the SSE/AVX version.

This is a prerequisite for D38714.

llvm-svn: 315797
2017-10-14 04:18:09 +00:00
Craig Topper 134241e4af [X86] Add AVX512 flavors of VCVTDQ2PD plus VCVTUDQ2PD to the load folding tables.
llvm-svn: 315796
2017-10-14 04:18:08 +00:00