11 Commits

Author	SHA1	Message	Date
Tom Stellard	9d7ddd516e	R600/SI: Start implementing an assembler ... This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. llvm-svn: 221994	2014-11-14 14:08:00 +00:00
Vincent Lejeune	4d5c5e53d0	R600: Use SchedModel enum for is{Trans,Vector}Only functions ... llvm-svn: 189979	2013-09-04 19:53:30 +00:00
Tom Stellard	f3d166aa1e	R600: Add support for i8 and i16 local memory stores ... llvm-svn: 189223	2013-08-26 15:05:49 +00:00
Tom Stellard	676c16d088	R600: Add IsExport bit to TableGen instruction definitions ... Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188516	2013-08-16 01:11:51 +00:00
Tom Stellard	4dd41845ec	Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions" ... This reverts commit 3f1de26cb5cc0543a6a1d71259a7a39d97139051. llvm-svn: 187524	2013-07-31 20:43:03 +00:00
Vincent Lejeune	79afe17e99	R600: Use SchedModel enum for is{Trans,Vector}Only functions ... llvm-svn: 187512	2013-07-31 19:31:35 +00:00
Tom Stellard	c026e8bc8e	R600: Add local memory support via LDS ... Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185162	2013-06-28 15:47:08 +00:00
Tom Stellard	5eb903d9c5	R600: Add ALUInst bit to tablegen definitions v2 ... v2: - Remove functions left over from a previous rebase. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185160	2013-06-28 15:46:53 +00:00
Tom Stellard	ecf9d86404	R600: Use correct encoding for Vertex Fetch instructions on Cayman ... Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 184016	2013-06-14 22:12:30 +00:00
Tom Stellard	d99b7932ae	R600: Factor the instruction encoding out the RAT_WRITE_CACHELESS_eg class ... Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 184014	2013-06-14 22:12:19 +00:00
Tom Stellard	3d0823f1cd	R600: Move instruction encoding definitions into a separate .td file ... Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 184013	2013-06-14 22:12:09 +00:00