If no bss sections appear after the relro segment, the loader will round
the r/w segment size to the target's page size. Align the relro size in the
same way to ensure that it does not extend past the end of the program's
own memory region.
Differential Revision: https://reviews.llvm.org/D29242
llvm-svn: 293519
To simplify/clarify memory ownership, make leaks (as one was found/fixed
recently) harder to write, etc.
(also, while I was there - removed a duplicate lookup in a container)
llvm-svn: 293506
This reverts commit r293196
Besides making things look nicer, ATM, we'd like to preserve analysis
more than we'd like to destroy the CFG. We'll probably revisit in the future
llvm-svn: 293501
The original shift is bigger, so this may qualify as 'obvious',
but here's an attempt at an Alive-based proof:
Name: exact
Pre: (C1 u< C2)
%a = shl i8 %x, C1
%b = lshr exact i8 %a, C2
=>
%c = lshr exact i8 %x, C2 - C1
%b = and i8 %c, ((1 << width(C1)) - 1) u>> C2
Optimization is correct!
llvm-svn: 293498
Original message:
Fix the values of two xcore ELF flags.
The values in llvm grew from a pre-MC day when they would not show up
in .o files and are outside of the SHF_MASKPROC.
Fortunately the MC output is not currently used as xcore has its own
assemble and that assembler uses valid values. This updates llvm to
use the same values as the xmos assembler.
llvm-svn: 293486
Different architectures can have different meaning for flags in the
SHF_MASKPROC mask, so we should always check what the architecture use
before checking the flag.
NFC for now, but will allow fixing the value of an xmos flag.
llvm-svn: 293484
Summary:
AMDGPU has two register classes with the same set of registers, and this
was causing this tablegen backend would get stuck in infinite recursion.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: tpr, wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D29049
llvm-svn: 293483
The values in llvm grew from a pre-MC day when they would not show up
in .o files and are outside of the SHF_MASKPROC.
Fortunately the MC output is not currently used as xcore has its own
assemble and that assembler uses valid values. This updates llvm to
use the same values as the xmos assembler.
llvm-svn: 293480
ld.bfd showed error on previous inputs, result values were larger than 8/16 bits,
though ld.gold accepted them.
ABI says "The R_386_16, and R_386_8 relocations truncate the computed
value to 16-bits and 8-bits respectively".
Patch changes inputs to have result calculated values of relocations to fit 8 and 16 bits.
That can be used for implementation of more strict checks, like bfd do.
Differential revision: https://reviews.llvm.org/D29270
llvm-svn: 293479
glibc < 2.18 is C99 compliant and only provides the format macros in C++ if
__STDC_FORMAT_MACROS is defined. This change fixes the debug build for
GCC 4.8, GCC 6.2 and Clang 3.9.1 that were previously broken on my machine.
It shows no regression for libc++ >= 4.0.0 which has a fix since September:
http://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20160926/171659.html
llvm-svn: 293468
Simon Pilgrim