Huihui Zhang
|
670778c762
|
[InstCombine] Fold icmp eq/ne (and %x, signbit), 0 -> %x s>=/s< 0 earlier
Summary:
To generate simplified IR, make sure fold
```
(X & signbit) ==/!= 0) -> X s>=/s< 0;
```
is scheduled before fold
```
((X << Y) & C) == 0 -> (X & (C >> Y)) == 0.
```
https://rise4fun.com/Alive/fbdh
Reviewers: lebedev.ri, efriedma, spatel, craig.topper
Reviewed By: lebedev.ri
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63026
llvm-svn: 363845
|
2019-06-19 17:31:39 +00:00 |
|
Huihui Zhang
|
dc2fd6a14e
|
[InstCombine] Add tests to show missing fold opportunity for "icmp and shift" (nfc).
Summary:
For icmp pred (and (sh X, Y), C), 0
When C is signbit, expect to fold (X << Y) & signbit ==/!= 0 into (X << Y) >=/< 0,
rather than (X & (signbit >> Y)) != 0.
When C+1 is power of 2, expect to fold (X << Y) & ~C ==/!= 0 into (X << Y) </>= C+1,
rather than (X & (~C >> Y)) == 0.
For icmp pred (and X, (sh signbit, Y)), 0
Expect to fold (X & (signbit l>> Y)) ==/!= 0 into (X << Y) >=/< 0
Expect to fold (X & (signbit << Y)) ==/!= 0 into (X l>> Y) >=/< 0
Reviewers: lebedev.ri, efriedma, spatel, craig.topper
Reviewed By: lebedev.ri
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63025
llvm-svn: 363479
|
2019-06-15 00:33:41 +00:00 |