Commit Graph

832 Commits

Author SHA1 Message Date
Daniel Sanders eab3146156 [mips] Range check simm11 and mem_simm11.
Summary:
ldc2/sdc2 now emit slightly worse diagnostics for MIPS-I. The problem
is that they don't trigger the custom parser because all the candidates
are disabled by feature bits. On all other subtargets, the diagnostics are
accurate but are subject to the usual issues of needing to report multiple
ways to correct the code (e.g. smaller offset, enable a CPU feature) but
only being able to report one error.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18436

llvm-svn: 265018
2016-03-31 14:23:20 +00:00
Daniel Sanders dc0602a2c2 [mips] Split mem_msa into range checked mem_simm10 and mem_simm10_lsl[123]
Summary:
Also, made test_mi10.s formatting consistent with the majority of the
MC tests.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18435

llvm-svn: 265014
2016-03-31 14:12:01 +00:00
Daniel Sanders 2e9f69d933 [mips] Range check simm9 and fix a bug this revealed.
Summary:
The bug was that microMIPS's [ls]w[lr]e instructions claimed to support a
12-bit offset when it is only 9-bit.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D18434

llvm-svn: 265010
2016-03-31 13:15:23 +00:00
Zlatko Buljan 6221be8e46 [mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructions
Differential Revision: http://reviews.llvm.org/D17334

llvm-svn: 265002
2016-03-31 08:51:24 +00:00
Simon Atanasyan 26fe92d19f [MC][mips] Add MipsMCInstrAnalysis class and register it as MC instruction analyzer
The `MipsMCInstrAnalysis` class overrides the `evaluateBranch` method
and calculates target addresses for branch and calls instructions.
That allows llvm-objdump to print functions' names in branch instructions
in the disassemble mode.

Differential Revision: http://reviews.llvm.org/D18209

llvm-svn: 264309
2016-03-24 17:18:14 +00:00
Simon Atanasyan b7807a0c8e [llvm-readobj] Decode st_other symbol's flags
The patch supports common STV_xxx visibility flags and MIPS specific
STO_MIPS_xxx flags.

Differential Revision: http://reviews.llvm.org/D18447

llvm-svn: 264300
2016-03-24 16:10:37 +00:00
Daniel Sanders 15f8fb6f83 [mips] Range check vsplat_simm5 and vsplat_simm10
Summary:

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D18177

llvm-svn: 264287
2016-03-24 14:53:40 +00:00
Daniel Sanders 837f15187b [mips] Range check simm10
Summary:

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D18148

llvm-svn: 264279
2016-03-24 13:26:59 +00:00
Zlatko Buljan 94af4cbcf4 [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions
Differential Revision: http://reviews.llvm.org/D17137

llvm-svn: 264248
2016-03-24 09:22:45 +00:00
Hrvoje Varga 2cb74ac3c3 [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructions
Differential Revision: http://reviews.llvm.org/D17328

llvm-svn: 264246
2016-03-24 08:02:09 +00:00
Daniel Sanders 97297770a6 [mips] Range check simm7.
Summary:
Also renamed li_simm7 to li16_imm since it's not a simm7 and has an unusual
encoding (it's a uimm7 except that 0x7f represents -1).

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18145

llvm-svn: 264056
2016-03-22 14:40:00 +00:00
Daniel Sanders 0f17d0da4a [mips] Range check simm5.
Summary:
We can't check the error message for this one because there's another lw/sw
available that covers a larger range. We therefore check the transition
between the two sizes.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D18144

llvm-svn: 264054
2016-03-22 14:29:53 +00:00
Daniel Sanders 946dee3b5b [mips] Range check vsplat_uimm[1234568].
Summary:

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18143

llvm-svn: 264053
2016-03-22 14:17:41 +00:00
Daniel Sanders 93fa4ce9b7 [mips] Range check uimm4_ptr, remove uimm6_ptr, and use correctly sized immediates in MSA copy/insert.
Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18142

llvm-svn: 264052
2016-03-22 13:58:53 +00:00
Simon Atanasyan 58ee875296 [mips] Use `formatImm` call to print immediate value in the `MipsInstPrinter`
That allows, for example, to print hex-formatted immediates using
llvm-objdump --print-imm-hex command line option.

Differential Revision: http://reviews.llvm.org/D18195

llvm-svn: 263704
2016-03-17 10:43:36 +00:00
Daniel Sanders 127d2d2b46 [mips] Range check uimm16_64
Summary:

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D17725

llvm-svn: 263427
2016-03-14 12:44:44 +00:00
Daniel Sanders 19b7f76afa [mips] Range check uimm6_lsl2.
Summary:

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D17291

llvm-svn: 263419
2016-03-14 11:16:56 +00:00
Daniel Sanders 78e8902097 [mips] Range check simm4.
Summary:

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D16811

llvm-svn: 263220
2016-03-11 11:37:50 +00:00
Hrvoje Varga 893c68cfc9 [mips] Invalid tests for MTC0, MTC2, MFC0, MFC2, DMTC0, DMFC0 MIPS instructions
Differential Revision: http://reviews.llvm.org/D18037

llvm-svn: 263203
2016-03-11 08:00:11 +00:00
Daniel Sanders 03a8d2f8ec [mips] Range check uimm20 and fixed a bug this revealed.
Summary:
The bug was that dextu's operand 3 would print 0-31 instead of 32-63 when
printing assembly. This came up when replacing
MipsInstPrinter::printUnsignedImm() with a version that could handle arbitrary
bit widths.

MipsAsmPrinter::printUnsignedImm*() don't seem to be used so they have been
removed.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D15521

llvm-svn: 262231
2016-02-29 16:06:38 +00:00
Daniel Sanders 611eb82953 [mips] Make isel select the correct DEXT variant up front.
Summary:
Previously, it would always select DEXT and substitute any invalid matches
for DEXTU/DEXTM during MipsMCCodeEmitter::encodeInstruction(). This works
but causes problems when adding range checked immediates to IAS.

Now isel selects the correct variant up front.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D16810

llvm-svn: 262229
2016-02-29 15:26:54 +00:00
Daniel Sanders 90f0d0b8e3 [mips] Make symbols an acceptable branch target when expanding compare-to-immediate-and-branch macros.
Reviewers: vkalintiris

Subscribers: llvm-commits, vkalintiris, dim, seanbruno, dsanders

Differential Revision: http://reviews.llvm.org/D15369

llvm-svn: 262213
2016-02-29 11:24:49 +00:00
Hrvoje Varga 46458d0bcc [mips][microMIPS] Implement DINSU, DINSM, DINS instructions
Differential Revision: http://reviews.llvm.org/D16181

llvm-svn: 261860
2016-02-25 12:53:29 +00:00
Zoran Jovanovic d665a66b0f [mips] added support for trunc macro
Author: obucina
Reviewers: dsanders
Differential Revision: http://reviews.llvm.org/D15745

llvm-svn: 261529
2016-02-22 16:00:23 +00:00
Zlatko Buljan f034021443 [mips][microMIPS] Implement TLBINV and TLBINVF instructions
Differential Revision: http://reviews.llvm.org/D16849

llvm-svn: 261211
2016-02-18 14:10:52 +00:00
Scott Egerton 219fae9e36 [mips] Removed the SHF_ALLOC flag and the SHT_REL flag from the .pdr section.
This section is used for debug information and has no need to be
in memory at runtime. This patch also fixes an error when compiling
the Linux kernel. The error is that there are relocations within the
.pdr section in a VDSO. SHT_REL was removed as it is a section type
and not a section flag, therefore it does not make sense for it to
be there. With this patch, LLVM now emits the same flags as
the GNU assembler.

llvm-svn: 261083
2016-02-17 11:15:16 +00:00
Scott Egerton d1aeb05654 [mips] Implemented the .hword directive.
Summary:
In order to pass the tests, this required marking R_MIPS_16 relocations
as needing to point to the symbol and not the section.

Reviewers: vkalintiris, dsanders

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D17200

llvm-svn: 260896
2016-02-15 16:11:51 +00:00
Scott Egerton 2c2a2f5119 Reverted r260879 as it caused test failures in lld.
llvm-svn: 260880
2016-02-15 10:04:38 +00:00
Scott Egerton baec95a88c [mips] Removed the SHF_ALLOC flag from the .pdr section.
Summary:
This section is used for debug information and has no need to be
in memory at runtime. With this patch, LLVM now emits the same flags as 
the GNU assembler. This patch also fixes an error when compiling 
the Linux kernel, The error is that there are relocations within the 
.pdr section in a VDSO.

Reviewers: vkalintiris, dsanders

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D17199

llvm-svn: 260879
2016-02-15 09:34:15 +00:00
Hrvoje Varga 02f99ea13d [mips][micromips] Written missing test for CEIL.L.S, CEIL.L.D, FLOOR.L.S and FLOOR.L.D instructions
Differential Revision: http://reviews.llvm.org/D17192

llvm-svn: 260673
2016-02-12 12:11:26 +00:00
Scott Egerton a1fa68ac9c [MC] Fixed parsing of macro arguments where expressions with spaces are present.
Summary:
Fixed an issue for mips with an instruction such as 'sdc1 $f1, 272 +8(a0)' which has a space between '272' and '+'. The parser would then parse '272' and '+8' as two arguments instead of a single expression resulting in one too many arguments in the pseudo instruction.
The reason that the test case has been changed is so that the expected
output matches the output of the GNU assembler.

Reviewers: vkalintiris, dsanders

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D13592

llvm-svn: 260521
2016-02-11 13:48:49 +00:00
Simon Atanasyan 2fc1e3b154 [mips] Extend MipsAsmParser class to handle %got(sym + const) expressions
Now the parser supports `%got(sym)` expressions only but `%got(sym + const)`
variant is also valid and accepted by GAS.

Differential Revision: http://reviews.llvm.org/D16885

llvm-svn: 260305
2016-02-09 22:31:49 +00:00
Daniel Sanders f8bb23e509 [mips] Range check uimm16 and fix several bugs this revealed.
Summary:
The bugs were:
* teq and similar take 4-bit unsigned immediates on microMIPS.
* teqi and similar have side-effects like teq do.
* shll_s.w and shra_r.w take 5-bit unsigned immediates.
* The various DSP ext* instructions take a 5-bit immediate.
* repl.qh takes an 8-bit unsigned immediate.
* repl.ph takes a 10-bit unsigned immediate.
* rddsp/wrdsp take a 10-bit unsigned immediate.
* teqi and similar take signed 16-bit immediates (10-bit for microMIPS).
* Out-of-range immediate macros for or/xor take a simm32/simm64 depending
  on architecture. I'll fix the simm64 case properly when I reach simm32.

lui is a bit more lenient than GAS and accepts signed immediates in addition
to unsigned. This is because MipsMCExpr can produce signed values when
constant folding and it currently lacks a way of knowing it should fold to
an unsigned value.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D15446

llvm-svn: 259360
2016-02-01 15:13:31 +00:00
Zoran Jovanovic d474ef3a3b [mips] Absolute value macro expansion
Author: obucina
Reviewers: dsanders
Differential Revision: http://reviews.llvm.org/D16323

llvm-svn: 259202
2016-01-29 16:18:34 +00:00
Scott Egerton 2455701117 [mips] Allowed dla instructions on 32-bit architectures.
Summary:
This is now the same as the behaviour of the GNU assembler. This was done
as it is required in order to build the Linux kernel with the integrated
assembler enabled.

Reviewers: dsanders, vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D13594

llvm-svn: 258400
2016-01-21 15:11:01 +00:00
David Majnemer ce10842036 [MC, COFF] Add .reloc support for WinCOFF
This adds rudimentary support for a few relocations that we will use for
the CodeView debug format.

llvm-svn: 258216
2016-01-19 23:05:27 +00:00
Daniel Sanders 4d32300cfd [mips] Never select JAL for calls to an absolute immediate address.
Summary:
It actually takes an offset into the current PC-region.

This fixes the 'expr' command in lldb.

Reviewers: vkalintiris, jaydeep, bhushan

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D16054

llvm-svn: 257339
2016-01-11 15:57:46 +00:00
Zlatko Buljan 5da2f6cd03 [mips][microMIPS] Implement DERET and DI instructions and check size operand for EXT and DEXT* instructions
Differential Revision: http://reviews.llvm.org/D15570

llvm-svn: 256152
2015-12-21 13:08:58 +00:00
Zlatko Buljan 252cca555f [mips][microMIPS][DSP] Implement PACKRL.PH, PICK.PH, PICK.QB, SHILO, SHILOV and WRDSP instructions
Differential Revision: http://reviews.llvm.org/D14429

llvm-svn: 255991
2015-12-18 08:59:37 +00:00
Daniel Sanders 3c7223133d [mips][ias] Range check uimm10 operands
Summary:

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D15229

llvm-svn: 255112
2015-12-09 13:48:05 +00:00
Zlatko Buljan 48f1f39bfe Revert r254897 "[mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions"
Commited patch was intended to implement LH, LHE, LHU and LHUE instructions.
After commit test-suite failed with error message in the form of:
fatal error: error in backend: Cannot select: t124: i32,ch = load<LD2[%d](tbaa=<0x94acc48>), sext from i16> t0, t2, undef:i32
For that reason I decided to revert commit r254897 and make new patch which besides implementation and standard regression tests will also have dedicated tests (CodeGen) for the above error. 

llvm-svn: 255109
2015-12-09 13:07:45 +00:00
Daniel Sanders 106d2d4693 [mips][ias] Range check uimm8 operands
Summary:

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D15226

llvm-svn: 255018
2015-12-08 14:42:10 +00:00
Daniel Sanders 59d092f883 [mips][ias] Range check uimm6 operands and fix a bug this revealed.
Summary:
We don't check the size operand on ext/dext*/ins/dins* yet because the
permitted range depends on the pos argument and we can't check that using
this mechanism.

The bug was that dextu/dinsu accepted 0..31 in the pos operand instead of 32..63.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D15190

llvm-svn: 255015
2015-12-08 13:49:19 +00:00
Daniel Sanders 1493e37f34 [mips][ias] Removed DSP/DSPr2 instructions from base architecture valid-xfail.s's.
Summary:
valid-xfail.s is for instructions that should be valid in the given ISA but
incorrectly fail. DSP/DSPr2 instructions are correct to fail since DSP/DSPr2 is
not enabled.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D15072

llvm-svn: 254911
2015-12-07 14:12:44 +00:00
Zlatko Buljan 1a01c15027 [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions
Differential Revision: http://reviews.llvm.org/D9824

llvm-svn: 254897
2015-12-07 08:29:31 +00:00
Zlatko Buljan 0f1223053c [mips][DSP] Add DSPr1 and DSPr2 tests for the standard encodings
Differential Revision: http://reviews.llvm.org/D15141

llvm-svn: 254598
2015-12-03 09:56:39 +00:00
Hrvoje Varga 672b0f5582 [mips][microMIPS] Implement PREPEND, RADDU.W.QB, RDDSP, REPL.PH, REPL.QB, REPLV.PH, REPLV.QB and MTHLIP instructions
Differential Revision: http://reviews.llvm.org/D14527

llvm-svn: 254496
2015-12-02 09:31:24 +00:00
Hrvoje Varga e51b0e13f3 [mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt, SEL.fmt, SELEQZ.fmt, SELNEQZ.fmt and CLASS.fmt
Differential Revision: http://reviews.llvm.org/D13885

llvm-svn: 254405
2015-12-01 11:59:21 +00:00
Hrvoje Varga c03957f049 [mips][microMIPS] Implement LBUX, LHX, LWX, MAQ_S[A].W.PHL, MAQ_S[A].W.PHR, MFHI, MFLO, MTHI and MTLO instructions
Differential Revision: http://reviews.llvm.org/D14436

llvm-svn: 254297
2015-11-30 12:58:39 +00:00
Zoran Jovanovic a887b36167 [mips][microMIPS] Fix issue with offset operand of BALC and BC instructions
Value of offset operand for microMIPS BALC and BC instructions is currently shifted 2 bits, but it should be 1 bit.
Differential Revision: http://reviews.llvm.org/D14770

llvm-svn: 254296
2015-11-30 12:56:18 +00:00
Daniel Sanders d32db286a0 [mips][ias] Removed MSA instructions from base architecture valid-xfail.s's.
valid-xfail.s is for instructions that should be valid in the given ISA but
incorrectly fail. MSA instructions are correct to fail since MSA is not enabled.

llvm-svn: 254293
2015-11-30 09:52:00 +00:00
Zlatko Buljan 56f3b0e410 [mips][microMIPS] Implement PRECR.QB.PH, PRECR_SRA[_R].PH.W, PRECRQ.PH.W, PRECRQ.QB.PH, PRECRQU_S.QB.PH and PRECRQ_RS.PH.W instructions
Differential Revision: http://reviews.llvm.org/D14605

llvm-svn: 254291
2015-11-30 08:37:38 +00:00
Daniel Sanders daa4b6fbd9 [mips][ias] Range check uimm5 operands and fix several bugs this revealed.
Summary:
The bugs were:
* append, prepend, and balign were not tested
* balign takes a uimm2 not a uimm5.
* drotr32 was correctly implemented with a uimm5 but the tests expected
  '52' to be valid.
* li/la were implemented with a uimm5 instead of simm32. simm32 isn't
  completely correct either but I'll fix that when I get to simm32.

A notable omission are some of the shift instructions. Several of these
have been implemented using a single uimm6 instruction (rather than two
uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated
in the uimm6 patch.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D14712

llvm-svn: 254164
2015-11-26 16:35:41 +00:00
Daniel Sanders 2b561336d9 [mips] .ent and .end should also set the type and size of the symbol respectively.
Reviewers: vkalintiris

Subscribers: llvm-commits, seanbruno, emaste, vkalintiris, dsanders

Differential Revision: http://reviews.llvm.org/D14221

llvm-svn: 253875
2015-11-23 16:08:03 +00:00
Hrvoje Varga b65518c15c [mips][microMIPS] Implement MUL[_S].PH, MULEQ_S.W.PHL, MULEQ_S.W.PHR, MULEU_S.PH.QBL, MULEU_S.PH.QBR, MULQ_RS.PH, MULQ_RS.W, MULQ_S.PH and MULQ_S.W instructions
Differential Revision: http://reviews.llvm.org/D14280

llvm-svn: 253651
2015-11-20 07:14:52 +00:00
Zoran Jovanovic 307f80eab1 [mips] Add tests for ROL and ROR macros expansion
Author: obucina
llvm-svn: 253567
2015-11-19 15:04:31 +00:00
Hrvoje Varga 78409019d9 [mips][microMIPS] Implement DPS.W.PH, DPSQ_S.W.PH, DPSQ_SA.L.W, DPSQX_S.W.PH, DPSQX_SA.W.PH, DPSU.H.QBL, DPSU.H.QBR and DPSX.W.PH instructions
Differential Revision: http://reviews.llvm.org/D14058

llvm-svn: 253443
2015-11-18 07:41:35 +00:00
Zlatko Buljan 72a7f9c1f5 [mips][microMIPS] Implement EXTP, EXTPDP, EXTPDPV, EXTPV, EXTR[_RS].W, EXTR_S.H, EXTRV[_RS].W and EXTRV_S.H instructions
Differential Revision: http://reviews.llvm.org/D14174

llvm-svn: 253332
2015-11-17 12:54:15 +00:00
Zlatko Buljan 246b21f66a [mips][microMIPS] Implement SUBQ[_S].PH, SUBQ_S.W, SUBQH[_R].PH, SUBQH[_R].W, SUBU[_S].PH, SUBU[_S].QB and SUBUH[_R].QB instructions
Differential Revision: http://reviews.llvm.org/D14114

llvm-svn: 253329
2015-11-17 10:11:22 +00:00
Oliver Stannard 9be59af3ab [Assembler] Make fatal assembler errors non-fatal
Currently, if the assembler encounters an error after parsing (such as an
out-of-range fixup), it reports this as a fatal error, and so stops after the
first error. However, for most of these there is an obvious way to recover
after emitting the error, such as emitting the fixup with a value of zero. This
means that we can report on all of the errors in a file, not just the first
one. MCContext::reportError records the fact that an error was encountered, so
we won't actually emit an object file with the incorrect contents.

Differential Revision: http://reviews.llvm.org/D14717

llvm-svn: 253328
2015-11-17 10:00:43 +00:00
Oliver Stannard 07b43d39a8 [Assembler] Allow non-fatal errors after parsing
This adds reportError to MCContext, which can be used as an alternative to
reportFatalError when the assembler wants to try to continue processing the
rest of the file after the error is reported, so that all of the errors ina
file can be reported. It records the fact that an error was encountered, so we
can avoid emitting an object file if any errors occurred.

This patch doesn't add any uses of this function (a later patch will convert
most uses of reportFatalError to use it), but there is a small functional
change: we use the SourceManager to print the error message, even if we have a
null SMLoc. This means that we get a SourceManager-style message, with the file
and line information shown as <unknown>, rather than the "LLVM ERROR" style
used by report_fatal_error.

llvm-svn: 253327
2015-11-17 09:58:07 +00:00
Zlatko Buljan 3e0588d033 [mips][microMIPS] Implement PRECEQ.W.PHL, PRECEQ.W.PHR, PRECEQU.PH.QBL, PRECEQU.PH.QBLA, PRECEQU.PH.QBR, PRECEQU.PH.QBRA, PRECEU.PH.QBL, PRECEU.PH.QBLA, PRECEU.PH.QBR and PRECEU.PH.QBRA instructions
Differential Revision: http://reviews.llvm.org/D14279

llvm-svn: 253326
2015-11-17 09:43:29 +00:00
Zlatko Buljan d1dea944b1 Added microMIPSDSPr1 assembler and disassembler tests to existing microMIPSDSPr2 test files.
llvm-svn: 253320
2015-11-17 07:58:27 +00:00
Zlatko Buljan 32fb5c40d2 [mips][microMIPS] Implement SHRA[_R].PH, SHRAV[_R].PH, SHRAV[_R].QB, SHRAV_R.W, SHRA_R.W, SHRL.PH, SHRL.QB, SHRLV.PH and SHRLV.QB instructions
Differential Revision: http://reviews.llvm.org/D14010

llvm-svn: 253041
2015-11-13 13:14:25 +00:00
Daniel Sanders 9f6ad49740 Implement .reloc (constant offset only) with support for R_MIPS_NONE and R_MIPS_32.
Summary:
Support for R_MIPS_NONE allows us to parse MIPS16's usage of .reloc.
R_MIPS_32 was included to be able to better test the directive.

Targets can add their relocations by overriding MCAsmBackend::getFixupKind().

Subscribers: grosbach, rafael, majnemer, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D13659

llvm-svn: 252888
2015-11-12 13:33:00 +00:00
Zlatko Buljan 797c2aec6b [mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructions
Differential Revision: http://reviews.llvm.org/D11406

llvm-svn: 252885
2015-11-12 13:21:33 +00:00
Daniel Sanders 70dd2d7ab9 [mips] Move MC tests for the DSP ASE into the standard format.
Summary:
Only DSPr2 is present because it appears we've never added DSPr1 tests.
We'll have to correct that in a later patch.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D14448

llvm-svn: 252752
2015-11-11 16:50:13 +00:00
Daniel Sanders 5762a4f9d1 [mips][ias] Range check uimm4 operands and fixed a bug this revealed.
Summary:
The bug was that the sldi instructions have immediate widths dependant on
their element size. So sldi.d has a 1-bit immediate and sldi.b has a 4-bit
immediate. All of these were using 4-bit immediates previously.

Reviewers: vkalintiris

Subscribers: llvm-commits, atanasyan, dsanders

Differential Revision: http://reviews.llvm.org/D14018

llvm-svn: 252297
2015-11-06 12:41:43 +00:00
Daniel Sanders 38ce0f629c [mips][ias] Range check uimm3 operands.
Summary:

Reviewers: vkalintiris

Subscribers: atanasyan, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D14016

llvm-svn: 252296
2015-11-06 12:31:27 +00:00
Daniel Sanders ea4f653d18 [mips][ias] Range check uimm2 operands and fix a bug this revealed.
Summary:
The bug was that the MIPS32R6/MIPS64R6/microMIPS32R6 versions of LSA and DLSA
(unlike the MSA version) failed to account for the off-by-one encoding of the
immediate. The range is actually 1..4 rather than 0..3.

Reviewers: vkalintiris

Subscribers: atanasyan, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D14015

llvm-svn: 252295
2015-11-06 12:22:31 +00:00
Daniel Sanders 52da7af4d2 [mips][ias] Range check uimmz operands.
Reviewers: vkalintiris

Subscribers: dsanders, atanasyan, llvm-commits

Differential Revision: http://reviews.llvm.org/D14013

llvm-svn: 252294
2015-11-06 12:11:03 +00:00
Rafael Espindola 56e0aafa2b Relax a few more overspecified tests.
llvm-svn: 251967
2015-11-03 19:38:19 +00:00
Hrvoje Varga 18148671ee [mips][microMIPS] Implement PAUSE, RDHWR, RDPGPR, SDBBP, SSNOP, SYNC, SYNCI and WAIT instructions
Differential Revision: http://reviews.llvm.org/D12628

llvm-svn: 251510
2015-10-28 11:04:29 +00:00
Zlatko Buljan 2cf61020b8 [mips][microMIPS] Implement SHLL.PH, SHLL_S.PH, SHLL.QB, SHLLV.PH, SHLLV_S.PH, SHLLV.QB, SHLLV_S.W, SHLL_S.W, SHRA.QB and SHRA_R.QB instructions
Differential Revision: http://reviews.llvm.org/D13929

llvm-svn: 251098
2015-10-23 06:39:29 +00:00
Daniel Sanders 0f596814e9 [mips][msa] Remove copy_u.d and move copy_u.w to MSA64.
Summary:
The forwards compatibility strategy employed by MIPS is to consider registers
to be infinitely sign-extended. Then on ISA's with a wider register, the result
of existing instructions are sign-extended to register width and zero-extended
counterparts are added. copy_u.w on MSA32 and copy_u.w on MSA64 violate this
strategy and we have therefore corrected the MSA specs to fix this.

We still keep track of sign/zero-extension during legalization but we now
match copy_s.[wd] where required.

No change required to clang since __builtin_msa_copy_u_[wd] will map to
copy_s.[wd] where appropriate for the target.

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13472

llvm-svn: 250887
2015-10-21 09:58:54 +00:00
Zlatko Buljan 5292083584 [mips][microMIPS] Implement ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB instructions
Differential Revision: http://reviews.llvm.org/D13130

llvm-svn: 250685
2015-10-19 07:16:26 +00:00
Zlatko Buljan d0a7d6e4ee [mips][microMIPS] Implement ABSQ.QB, ABSQ_S.PH, ABSQ_S.W, ABSQ_S.QB, INSV, MADD, MADDU, MSUB, MSUBU, MULT and MULTU instructions
Differential Revision: http://reviews.llvm.org/D13721

llvm-svn: 250683
2015-10-19 06:34:44 +00:00
Zlatko Buljan 4c4f21b971 Commited two test files which are forgotten during commit of patch for http://reviews.llvm.org/D13376
llvm-svn: 250512
2015-10-16 13:03:10 +00:00
Hrvoje Varga 3c88fbd367 [mips][microMIPS] Implement LB, LBE, LBU and LBUE instructions
Differential Revision: http://reviews.llvm.org/D11633

llvm-svn: 250511
2015-10-16 12:24:58 +00:00
Daniel Sanders 6394ee598e [mips][ias] Implement ulh macro.
Summary:
This macro is needed to prevent test/CodeGen/Mips/2008-08-01-AsmInline.ll from
failing after the integrated assembler is enabled by default.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D13654

llvm-svn: 250414
2015-10-15 14:52:58 +00:00
Zlatko Buljan 54b1eb4c73 [mips][microMIPS] Implement DPA.W.PH, DPAQ_S.W.PH, DPAQ_SA.L.W, DPAQX_S.W.PH, DPAQX_SA.W.PH, DPAU.H.QBL, DPAU.H.QBR and DPAX.W.PH instructions
Differential Revision: http://reviews.llvm.org/D13376

llvm-svn: 250382
2015-10-15 08:59:45 +00:00
Hrvoje Varga 3a3c4b8a39 [mips][microMIPS] Implement BREAK16, LI16, MOVE16, SDBBP16, SUBU16 and XOR16 instructions
Differential Revision: http://reviews.llvm.org/D11292#inline-103143

llvm-svn: 250381
2015-10-15 08:39:07 +00:00
Hrvoje Varga 3ef4dd7bc8 [mips][microMIPS] Implement LLE and SCE instructions
Differential Revision: http://reviews.llvm.org/D11630

llvm-svn: 250379
2015-10-15 08:11:50 +00:00
Hrvoje Varga a766eff5a0 [mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructions
Differential Revision: http://reviews.llvm.org/D11631

llvm-svn: 250377
2015-10-15 07:23:06 +00:00
Zoran Jovanovic 2e386d3d07 [mips][micromips] Initial support for micrmomips DSP instructions and addu.qb implementation
Differential Revision: http://reviews.llvm.org/D12798

llvm-svn: 250058
2015-10-12 16:07:25 +00:00
Daniel Sanders b1ef88c172 [mips][ias] Implement macro expansion when bcc has an immediate where a register belongs.
Summary: Fixes PR24915.

Reviewers: vkalintiris

Subscribers: emaste, seanbruno, llvm-commits

Differential Revision: http://reviews.llvm.org/D13533

llvm-svn: 250042
2015-10-12 14:24:05 +00:00
Zoran Jovanovic 5a8dffc618 [mips][microMIPS] Implement JALRC16, JRCADDIUSP and JRC16 instructions
Differential Revision: http://reviews.llvm.org/D11219

llvm-svn: 249317
2015-10-05 14:00:09 +00:00
Daniel Sanders d5a89418c5 [mips] Changed the way symbols are handled in dla and la instructions to allow simple expressions.
Summary:
An instruction like "(d)la $5, symbol+8" previously would have crashed the
assembler as it contains an expression. This is now fixed.
A few tests cases have also been changed to reflect these changes, however
these should only be syntax changes. Some new test cases have also been
added.

Patch by Scott Egerton.

Reviewers: vkalintiris, dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12760

llvm-svn: 249311
2015-10-05 13:19:29 +00:00
Zoran Jovanovic 2960f3a346 [mips][microMIPS] Implement CACHEE, WRPGPR and WSBH instructions
Differential Revision: http://reviews.llvm.org/D10337

llvm-svn: 249004
2015-10-01 12:49:27 +00:00
Zoran Jovanovic cdb64566cc [mips] Handling of immediates bigger than 16 bits
Differential Revision: http://reviews.llvm.org/D10539

llvm-svn: 248706
2015-09-28 11:11:34 +00:00
Rafael Espindola 4405d5d889 Use ELFOSABI_NONE instead of ELFOSABI_LINUX.
The doesn't seem to be a difference and ELFOSABI_NONE seems to be far more
common:

* Linux doesn't care when loading and puts ELFOSABI_NONE on core dumps.
* Gold and bfd ld produce files with ELFOSABI_NONE.
* Gold and bfd ld seems to ignore EI_OSABI other than for freebsd.
* Gas puts ELFOSABI_NONE in most .o files.

llvm-svn: 248534
2015-09-24 20:57:24 +00:00
Daniel Sanders f173dda0e2 [mips][ias] Implement .cpreturn directive.
Summary:
Based on a patch by David Chisnall. I've modified the original patch as follows:
* Moved the expansion to the TargetStreamers so that the directive isn't
  expanded when emitting assembly.
* Fixed an operand order bug.
* Changed the move instructions from DADDu to OR to match recent changes to GAS.

Reviewers: vkalintiris

Subscribers: llvm-commits, emaste, seanbruno, theraven

Differential Revision: http://reviews.llvm.org/D13017

llvm-svn: 248258
2015-09-22 10:50:09 +00:00
Daniel Sanders 5d7962880d [mips] Allow constant expressions in second argument of .cpsetup.
Summary:
Also tightened up the test and made a trivial fix to prevent double-newline
after emitting .cpsetup directives.

Reviewers: vkalintiris

Subscribers: seanbruno, emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D12956

llvm-svn: 248143
2015-09-21 09:26:55 +00:00
Daniel Sanders e2982adc0b [mips] Add assembler support for the .cprestore directive.
Summary:
This assembler directive is used in O32 PIC to restore the current function's $gp after executing JAL's. The $gp is first stored on the stack at a user-specified offset.
It has the following format: ".cprestore 8" (where 8 is the offset).

This fixes llvm.org/PR20967.

Patch by Toma Tabacu.

Reviewers: seanbruno, tomatabacu

Subscribers: brooks, seanbruno, emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D6267

llvm-svn: 247897
2015-09-17 16:08:39 +00:00
Zoran Jovanovic 7ba636cb4c [mips][microMIPS] Implement TEQ, TGE, TGEU, TLT, TLTU and TNE instructions
Differential Revision: http://reviews.llvm.org/D9658

llvm-svn: 247880
2015-09-17 10:14:09 +00:00
Zoran Jovanovic 6e6a2c9cd7 [mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and SWE instructions
Differential Revision: http://reviews.llvm.org/D9189

llvm-svn: 247780
2015-09-16 09:14:35 +00:00
Zoran Jovanovic 8eb8c9861d [mips] Add support for branch-likely pseudo-instructions
Differential Revision: http://reviews.llvm.org/D10537

llvm-svn: 247697
2015-09-15 15:06:26 +00:00
Zoran Jovanovic 7beb737b46 [mips][microMIPS] Implement CACHEE and PREFE instructions for microMIPS32r6
Differential Revision: http://reviews.llvm.org/D11632

llvm-svn: 247670
2015-09-15 10:05:10 +00:00
Daniel Sanders e4e83a7bc1 [mips] Added support for various EVA ASE instructions.
Summary:
Added support for the following instructions:

CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF

This required adding some infrastructure for the EVA ASE.

Patch by Scott Egerton.

Reviewers: vkalintiris, dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11139

llvm-svn: 247669
2015-09-15 10:02:16 +00:00
Zoran Jovanovic 6b28f09d67 [mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instructions
Differential Revision: http://reviews.llvm.org/D11178

llvm-svn: 247146
2015-09-09 13:55:45 +00:00
Zoran Jovanovic d9790793d6 [mips][microMIPS] Implement CACHEE and PREFE instructions
Differential Revision: http://reviews.llvm.org/D11628

llvm-svn: 247125
2015-09-09 09:10:46 +00:00
Zoran Jovanovic 2da1437d62 [mips][microMIPS] Implement LLE, LUI, LW and LWE instructions
Differential Revision: http://reviews.llvm.org/D1179

llvm-svn: 247017
2015-09-08 15:02:50 +00:00
Zoran Jovanovic 9eaa30d2bf [mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructions
Differential Revision: http://reviews.llvm.org/D11801

llvm-svn: 246999
2015-09-08 10:18:38 +00:00
Zoran Jovanovic 68be5f21a9 [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit LBU16, LHU16, LW16, LWGP and LWSP instructions
Differential Revision: http://reviews.llvm.org/D10956

llvm-svn: 246987
2015-09-08 08:25:34 +00:00
Zoran Jovanovic 7b85682541 [mips][microMIPS] Implement ABS.fmt, CEIL.L.fmt, CEIL.W.fmt, FLOOR.L.fmt, FLOOR.W.fmt, TRUNC.L.fmt, TRUNC.W.fmt, RSQRT.fmt and SQRT.fmt instructions
Differential Revision: http://reviews.llvm.org/D11674

llvm-svn: 246968
2015-09-07 13:01:04 +00:00
Zoran Jovanovic ada7091812 [mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructions
Differential Revision: http://reviews.llvm.org/D11181

llvm-svn: 246963
2015-09-07 11:56:37 +00:00
Zoran Jovanovic 14f308e44f [mips][microMIPS] Implement CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, MAX.fmt, MIN.fmt, MAXA.fmt, MINA.fmt and CMP.condn.fmt instructions
Differential Revision: http://reviews.llvm.org/D12141

llvm-svn: 246960
2015-09-07 10:31:31 +00:00
Zoran Jovanovic 89ca2b982e [mips][microMIPS] Implement ADD.fmt, SUB.fmt, MOV.fmt, MUL.fmt, DIV.fmt, MADDF.fmt, MSUBF.fmt and NEG.fmt instructions
Differential Revision: http://reviews.llvm.org/D11978

llvm-svn: 246919
2015-09-05 09:25:30 +00:00
Daniel Sanders 3ebcaf6685 [mips] Added support for the div, divu, ddiv and ddivu macros which use traps and breaks in the integrated assembler.
Summary:

Patch by Scott Egerton

Reviewers: vkalintiris, dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11675

llvm-svn: 246763
2015-09-03 12:31:22 +00:00
Zoran Jovanovic 56585d517b [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit ADDIUR1SP, ADDIUR2, ADDIUS5 and ADDIUSP instructions
Differential Revision: http://reviews.llvm.org/D10955

llvm-svn: 245554
2015-08-20 11:51:49 +00:00
Daniel Sanders 63f4a5dcad [mips] Expand JAL instructions when PIC is enabled.
Summary: This is the correct way to handle JAL instructions when PIC is enabled.

Patch by Toma Tabacu

Reviewers: seanbruno, tomatabacu

Subscribers: brooks, seanbruno, emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D6231

llvm-svn: 245305
2015-08-18 16:18:09 +00:00
Zoran Jovanovic 2fe8466f6e [mips][microMIPS] Implement DDIV, DMOD, DDIVU and DMODU instructions
Differential Revision: http://reviews.llvm.org/D10953

llvm-svn: 245297
2015-08-18 14:40:43 +00:00
Zoran Jovanovic a6593ff613 [mips][microMIPS] Implement SW and SWE instructions
Differential Revision: http://reviews.llvm.org/D10869

llvm-svn: 245293
2015-08-18 12:53:08 +00:00
Daniel Sanders a39ef1c68f [mips] [IAS] Add support for the DLA pseudo-instruction and fix problems with DLI
Summary: It is the same as LA, except that it can also load 64-bit addresses and it only works on 64-bit MIPS architectures.

Reviewers: tomatabacu, seanbruno, vkalintiris

Subscribers: brooks, seanbruno, emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D9524

llvm-svn: 245208
2015-08-17 10:11:55 +00:00
Vasileios Kalintiris 1c78ca6a09 [mips] Remap move as or.
Summary:
This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or
'addu'. The use of addu/daddu instead of or as move was highlighted as a
performance issue during the analysis of a recent 64bit design. Originally
move was encoded as 'or' by binutils but was changed for the r10k cpu family
due to their pipeline which had 2 arithmetic units and a single logical unit,
and so could issue multiple (d)addu based moves at the same time but only 1
logical move.

This patch preserves the disassembly behaviour so that disassembling a old style
(d)addu move still appears as move, but assembling move always gives an or

Patch by Simon Dardis.

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11796

llvm-svn: 244579
2015-08-11 08:56:25 +00:00
Vasileios Kalintiris 974d409259 [mips] Added support for the ERETNC instruction.
Summary: This required adding the instruction predicate HasMips32r5.

Patch by Scott Egerton.

Reviewers: dsanders, vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11136

llvm-svn: 242666
2015-07-20 12:28:56 +00:00
Daniel Sanders 03f9c019d2 [mips] Fix li/la differences between IAS and GAS.
Summary:
- Signed 16-bit should have priority over unsigned.
- For la, unsigned 16-bit must use ori+addu rather than directly use ori.
- Correct tests on 32-bit immediates with 64-bit predicates by
  sign-extending the immediate beforehand. For example, isInt<16>(0xffff8000)
  should be true and use addiu.

Also split li/la testing into separate files due to their size.

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10967

llvm-svn: 242139
2015-07-14 12:24:22 +00:00
Zoran Jovanovic 2a47d08afd [mips][microMIPS] Implement SLL and NOP instructions
http://reviews.llvm.org/D10474

llvm-svn: 241150
2015-07-01 09:54:51 +00:00
Toma Tabacu 0f09313051 [mips] [IAS] Add support for the .module softfloat/hardfloat directives.
These directives are used to set the default value of the SoftFloat feature.
They have the same effect as setting -m{soft, hard}-float from the command line.

Differential Revision: http://reviews.llvm.org/D9073

llvm-svn: 241066
2015-06-30 13:46:03 +00:00
Toma Tabacu fc97d8a95a [mips] [IAS] Make .module directives change AssemblerOptions->front().
Differential Revision: http://reviews.llvm.org/D10643

llvm-svn: 241062
2015-06-30 12:41:33 +00:00
Toma Tabacu 32c72aa099 [mips] [IAS] Add support for the .set oddspreg/nooddspreg directives.
Differential Revision: http://reviews.llvm.org/D10657

llvm-svn: 241052
2015-06-30 09:36:50 +00:00
Daniel Sanders a3134fae17 [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.
Summary:
Previously it (incorrectly) used GPR's.

Patch by Simon Dardis. A couple small corrections by myself.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10567

llvm-svn: 240883
2015-06-27 15:39:19 +00:00
Toma Tabacu 0a6fa59a2c [mips] [IAS] Add partial support for the ULW pseudo-instruction.
Summary:
This only adds support for ULW of an immediate address with/without a source register.
It does not include support for ULW of the address of a symbol.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9663

llvm-svn: 240782
2015-06-26 13:20:17 +00:00
Toma Tabacu 7bc44dcb0c [mips] [IAS] Fix parsing of memory offset expressions with parenthesis depth >1.
Summary:
In an expression such as "(((a+b)+c)+d)", parseParenExpression() would only parse the "a+b)+c", which would result in an error later on in the parser.
This means that we can only parse one level of inner parentheses.

In order to fix this, I added a new function called parseParenExprOfDepth(), which parses a specified number of trailing parenthesis expressions
(except for the outermost parenthesis), and changed MipsAsmParser to use it in parseMemOffset instead of parseParenExpression().

Reviewers: dsanders, rafael

Reviewed By: dsanders, rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9742

llvm-svn: 240625
2015-06-25 09:52:02 +00:00
Zoran Jovanovic 67e04be640 [mips][microMIPS] Implement BREAK, EHB and EI instructions
http://reviews.llvm.org/D10090

llvm-svn: 240531
2015-06-24 10:32:16 +00:00
Toma Tabacu d88d79c79d [mips] [IAS] Add partial support for the ULHU pseudo-instruction.
Summary:
This only adds support for ULHU of an immediate address with/without a source register.
It does not include support for ULHU of the address of a symbol.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9671

llvm-svn: 240410
2015-06-23 14:39:42 +00:00
Petar Jovanovic b7915a1f0b [mips64] Emit correct addend for some PC-relative relocations
So far, LLVM has not emitted correct addend for N64 and N32 ABI. This patch
fixes that. It also removes fixup from MCJIT for R_MIPS_PC16 relocation.

Patch by Vladimir Radosavljevic.

Differential Revision: http://reviews.llvm.org/D10565

llvm-svn: 240404
2015-06-23 13:54:42 +00:00
Daniel Jasper 41de8027b1 Revert r240302 ("Bring r240130 back.").
This causes errors like:

  ld: error: blah.o: requires dynamic R_X86_64_PC32 reloc against '' which
  may overflow at runtime; recompile with -fPIC
  blah.cc:function f(): error: undefined reference to ''
  blah.o:g(): error: undefined reference to ''

I have not yet come up with an appropriate reproduction.

llvm-svn: 240394
2015-06-23 11:31:32 +00:00
Daniel Sanders 70b5908d39 [mips] llvm-readobj can parse .MIPS.abiflags. No need to check the bytes.
Summary:

Reviewers: atanasyan

Reviewed By: atanasyan

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10538

llvm-svn: 240392
2015-06-23 10:11:36 +00:00
Rafael Espindola 2d6bae2e09 Bring r240130 back.
Now that pr23900 is fixed, we can bring it back with no changes.

Original message:

Make all temporary symbols unnamed.

What this does is make all symbols that would otherwise start with a .L
(or L on MachO) unnamed.

Some of these symbols still show up in the symbol table, but we can just
make them unnamed.

In order to make sure we produce identical results when going thought assembly,
all .L (not just the compiler produced ones), are now unnamed.

Running llc on llvm-as.opt.bc, the peak memory usage goes from 208.24MB to
205.57MB.

llvm-svn: 240302
2015-06-22 17:52:52 +00:00
Toma Tabacu 8e0316d439 [mips] [IAS] Add support for LAReg with identical source and destination register operands.
Summary: In this case, we're supposed to load the immediate in AT and then ADDu it with the source register and put it in the destination register.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9367

llvm-svn: 240278
2015-06-22 13:10:23 +00:00
Toma Tabacu fb9d125592 [mips] [IAS] Add support for LASym with identical source and destination register operands.
Summary:
In this case, we're supposed to load the address of the symbol in AT and then ADDu it with the source register and
put it in the destination register.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9366

llvm-svn: 240273
2015-06-22 12:08:39 +00:00
Nico Weber 67e715ff7d Revert 240130, it caused crashes (repro in PR23900).
llvm-svn: 240193
2015-06-19 23:43:47 +00:00
Rafael Espindola 284a750c5f Make all temporary symbols unnamed.
What this does is make all symbols that would otherwise start with a .L
(or L on MachO) unnamed.

Some of these symbols still show up in the symbol table, but we can just
make them unnamed.

In order to make sure we produce identical results when going thought assembly,
all .L (not just the compiler produced ones), are now unnamed.

Running llc on llvm-as.opt.bc, the peak memory usage goes from 208.24MB to
205.57MB.

llvm-svn: 240130
2015-06-19 12:16:55 +00:00
Benjamin Kramer 58675d4f84 [MC/Dwarf] Encode DW_CFA_advance_loc in target endianess.
This matches GNU as output.

llvm-svn: 239911
2015-06-17 15:14:35 +00:00
Toma Tabacu f712ede932 [mips] [IAS] Add support for expanding LASym with a source register operand.
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9348

llvm-svn: 239910
2015-06-17 14:31:51 +00:00
Toma Tabacu 1a1083285c [mips] [IAS] Add support for the B{L,G}{T,E}(U) branch pseudo-instructions.
Summary:
This does not include support for the immediate variants of these pseudo-instructions.
Fixes llvm.org/PR20968.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: seanbruno, emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D8537

llvm-svn: 239905
2015-06-17 13:20:24 +00:00
Toma Tabacu 9e7b90c244 [mips] [IAS] Fix LA with relative label operands.
Summary:
Call MCSymbolRefExpr::create() with a MCSymbol* argument, not with a StringRef
of the Symbol's name, in order to avoid creating invalid temporary symbols for
relative labels (e.g. {$,.L}tmp00, {$,.L}tmp10 etc.).

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10498

llvm-svn: 239901
2015-06-17 12:30:37 +00:00
Toma Tabacu 6a1e0eb27d [mips] [IAS] Add test for SW with relative label operands. NFC.
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10497

llvm-svn: 239899
2015-06-17 11:46:37 +00:00
Toma Tabacu 07c97b3b7e [mips] [IAS] Fix LW with relative label operands.
Summary:
Previously, MCSymbolRefExpr::create() was called with a StringRef of the symbol
name, which it would then search for in the Symbols StringMap (from MCContext).

However, relative labels (which are temporary symbols) are apparently not stored
in the Symbols StringMap, so we end up creating a new {$,.L}tmp symbol
({$,.L}tmp00, {$,.L}tmp10 etc.) each time we create an MCSymbolRefExpr by
passing in the symbol name as a StringRef.

Fortunately, there is a version of MCSymbolRefExpr::create() which takes an
MCSymbol* and we already have an MCSymbol* at that point, so we can just pass
that in instead of the StringRef.

I also removed the local StringRef calls to MCSymbolRefExpr::create() from
expandMemInst(), as those cases can be handled by evaluateRelocExpr() anyway.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9938

llvm-svn: 239897
2015-06-17 10:43:45 +00:00
Daniel Sanders 58405d856e [mips][ias] Expand on r238751 to cover as many relocs as possible.
Summary:
Relocs that can be converted from absolute to PC-relative now do so if IsPCRel
is true. Relocs that require PC-relative now call llvm_unreachable() if IsPCRel
is false and similarly those that require absolute assert that IsPCRel is false.

Note that while it looks like some relocs (e.g. R_MIPS_26) can be converted into
the MIPS32r6/MIPS64r6 relocs (R_MIPS_PC*_S2), it isn't actually valid to do so.

Placeholders have been left in the testcase for unsupported relocs and relocs
that cannot be generated at the moment.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits, rafael

Differential Revision: http://reviews.llvm.org/D10184

llvm-svn: 239817
2015-06-16 13:46:26 +00:00
Toma Tabacu e1e460dbc5 Recommit "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." (r239396).
Apparently, Arcanist didn't include some of my local changes in my previous
commit attempt.

llvm-svn: 239523
2015-06-11 10:36:10 +00:00
Zoran Jovanovic cdfcbe41f2 [mips][microMIPS] Implement ERET and ERETNC instructions
http://reviews.llvm.org/D10091

llvm-svn: 239522
2015-06-11 10:22:46 +00:00
Zoran Jovanovic 6b0dcd7b8c [mips] Change existing uimm10 operand to restrict the accepted immediates
http://reviews.llvm.org/D10312

llvm-svn: 239520
2015-06-11 09:51:58 +00:00
Toma Tabacu 465acfd13c Recommit "[mips] [IAS] Restore STI.FeatureBits in .set pop." (r239144).
Specified the llvm namespace for the 2 calls to make_unique() which caused
compilation errors in Visual Studio 2013.

llvm-svn: 239405
2015-06-09 13:33:26 +00:00
Toma Tabacu 7977cfd52a Revert "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." (r239396).
It was breaking buildbots.

llvm-svn: 239397
2015-06-09 10:43:49 +00:00
Toma Tabacu 5fa8fb5762 [mips] [IAS] Add support for BNE and BEQ with an immediate operand.
Summary:
For some branches, GAS accepts an immediate instead of the 2nd register operand.
We only implement this for BNE and BEQ for now. Other branch instructions can be added later, if needed.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: seanbruno, emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D9666

llvm-svn: 239396
2015-06-09 10:34:31 +00:00
Toma Tabacu 399a56d771 Revert "[mips] [IAS] Restore STI.FeatureBits in .set pop." (r239144).
This is breaking the Windows buildbots.

llvm-svn: 239145
2015-06-05 12:19:27 +00:00
Toma Tabacu 89ebf88ff3 [mips] [IAS] Restore STI.FeatureBits in .set pop.
Summary:
Only restoring AvailableFeatures is not enough and will lead to buggy behaviour.
For example, if we have a feature enabled and we ".set pop", the next time we try
to ".set" that feature nothing will happen because the "!(STI.getFeatureBits()[Feature])"
check will be false, because we didn't restore STI.FeatureBits.

In order to fix this, we need to make MipsAssemblerOptions remember the STI.FeatureBits
instead of the AvailableFeatures and then regenerate AvailableFeatures each time we ".set pop".
This is because, AFAIK, there is no way to convert from AvailableFeatures back to STI.FeatureBits,
but the reverse is possible by using ComputeAvailableFeatures(STI.FeatureBits).

I also moved the updating of AssemblerOptions inside the "if" statement in
setFeatureBits() and clearFeatureBits(), as there is no reason to update if
nothing changes.

Reviewers: dsanders, mkuper

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9156

llvm-svn: 239144
2015-06-05 11:48:54 +00:00
Rafael Espindola 20733034a7 llvm-readobj can parse relocations, no need to check the raw bytes.x
llvm-svn: 239041
2015-06-04 15:15:12 +00:00
Toma Tabacu c15dd736f8 [mips] [IAS] Reformat mips-expansions.s. NFC.
Summary:
Make mips-expansions.s more readable by grouping the instructions with their respective CHECK's.
This test is going to get a lot bigger soon and it will become essentially unreadable if the current formatting is kept.

I've also made the comments more useful and accurate, and I've restricted the RUN lines to under 80 columns.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10089

llvm-svn: 238817
2015-06-02 10:34:10 +00:00
Daniel Sanders f87702112d [mips] Test both %dtprel_hi and %dtprel_lo instead of testing %dtprel_hi twice.
The second %dtprel_hi is used on an addiu so it looks like a copy/paste error.

llvm-svn: 238815
2015-06-02 10:09:08 +00:00
Daniel Sanders 4d652b8a2d [mips] Expand tabs in test/MC/Mips/mips-relocations.s
llvm-svn: 238814
2015-06-02 10:02:00 +00:00
Toma Tabacu 2969650ecd [mips] [IAS] Add support for the .set softfloat/hardfloat directives.
Summary: These directives are used to set the current value of the SoftFloat feature.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits, mpf

Differential Revision: http://reviews.llvm.org/D9074

llvm-svn: 238813
2015-06-02 09:48:04 +00:00
Rafael Espindola 7f7caf9167 Fix relocation selection for foo-. on mips.
This handles only the 32 bit case.

llvm-svn: 238751
2015-06-01 15:10:51 +00:00
Kai Nacke 3adf9b8d80 [mips] Add new format for dmtc2/dmfc2 for Octeon CPUs.
Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor.
E.g. dmtc2 rt,0x4057 starts calculation of sha-1.

I had to introduce a new deconding namespace to avoid a decoding conflict.

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D10083

llvm-svn: 238439
2015-05-28 16:23:16 +00:00
Zoran Jovanovic 85a53a1ed5 [mips][microMIPSr6] Implement SEB and SEH instructions
Differential Revision: http://reviews.llvm.org/D9739

llvm-svn: 238333
2015-05-27 15:39:47 +00:00
Jozef Kolek 888830adfe [mips][microMIPSr6] Implement BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC and BNEZALC instructions
This patch implements microMIPS32r6 BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC
and BNEZALC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D10031

llvm-svn: 238325
2015-05-27 14:19:22 +00:00
Rafael Espindola 95ee81daf6 Relax these tests a bit.
It is not relevant where in the string table the name is located.

llvm-svn: 238053
2015-05-22 21:37:13 +00:00
Toma Tabacu 1e0a69f222 [mips] [IAS] Add 2 missing CHECK directives for fixups in mips-expansions.s.
llvm-svn: 237884
2015-05-21 10:04:39 +00:00
Zoran Jovanovic dde61c00c3 [mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructions
Differential Revision: http://reviews.llvm.org/D8800

llvm-svn: 237697
2015-05-19 14:12:55 +00:00
Zoran Jovanovic 299fed6b7d [mips][microMIPSr6] Implement AND and ANDI instructions
Differential Revision: http://reviews.llvm.org/D8772

llvm-svn: 237696
2015-05-19 13:32:31 +00:00
Zoran Jovanovic 3825261572 [mips][microMIPSr6] Implement DIV, DIVU, MOD and MODU instructions
Differential Revision: http://reviews.llvm.org/D8769

llvm-svn: 237685
2015-05-19 11:21:37 +00:00
Jozef Kolek cc0c0fc926 [mips][microMIPSr6] Implement LSA instruction
This patch implements LSA instruction using mapping.

Differential Revision: http://reviews.llvm.org/D8919

llvm-svn: 237634
2015-05-18 23:12:10 +00:00
Jozef Kolek cbb227b48d [mips][microMIPSr6] Implement ALIGN and AUI instructions
This patch implements ALIGN and AUI instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8782

llvm-svn: 237563
2015-05-18 11:44:30 +00:00
Toma Tabacu a3d056fd4c [mips] [IAS] Fix expansion of negative 32-bit immediates for LI/DLI.
Summary:
To maintain compatibility with GAS, we need to stop treating negative 32-bit immediates as 64-bit values when expanding LI/DLI.
This currently happens because of sign extension.

To do this we need to choose the 32-bit value expansion for values which use their upper 33 bits only for sign extension (i.e. no 0's, only 1's).

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8662

llvm-svn: 237428
2015-05-15 09:42:11 +00:00
Toma Tabacu e625b5fc02 [mips] [IAS] Enforce .set nomacro.
Summary: When used, ".set nomacro" causes warning messages to be reported when we expand pseudo-instructions to multiple machine instructions.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9564

llvm-svn: 237366
2015-05-14 14:51:32 +00:00
Toma Tabacu 772155cbc6 [mips] [IAS] Emit .set macro/nomacro.
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9563

llvm-svn: 237363
2015-05-14 13:42:10 +00:00
Toma Tabacu ec1de82213 [mips] [IAS] Warn when LA is used with a 64-bit symbol.
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9295

llvm-svn: 237356
2015-05-14 10:53:40 +00:00
Jozef Kolek 6fec325d10 [mips][microMIPSr6] Implement CLO and CLZ instructions
This patch implements CLO and CLZ instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8553

llvm-svn: 237257
2015-05-13 14:18:11 +00:00
Toma Tabacu d0a7ff2ed7 [mips] [IAS] Unify common functionality of LA and LI.
Summary: A side-effect of this is that LA gains proper handling of unsigned and positive signed 16-bit immediates and more accurate error messages.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9290

llvm-svn: 237255
2015-05-13 13:56:16 +00:00
Toma Tabacu 9fb2ff71ca [mips] [IAS] Merge the micromips-expressions.s test into expr1.s. NFC.
Summary: Also did some minor reformatting in the resulting test.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9702

llvm-svn: 237242
2015-05-13 09:53:53 +00:00
Jozef Kolek 38bb81db85 [mips][microMIPSr6] Implement SELEQZ and SELNEZ instructions
This patch implements SELEQZ and SELNEZ instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8497

llvm-svn: 237158
2015-05-12 17:39:32 +00:00
Jozef Kolek 8abad7bacc [mips][microMIPSr6] Implement ALUIPC and AUIPC instructions
This patch implements ALUIPC and AUIPC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8441

llvm-svn: 236858
2015-05-08 14:25:11 +00:00
Jozef Kolek 9ce6e0a926 [mips][microMIPSr6] Implement ADDIUPC and LWPC instructions
This patch implements ADDIUPC and LWPC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8415

llvm-svn: 236852
2015-05-08 13:52:04 +00:00
Jozef Kolek cf98462818 [mips][microMIPSr6] Implement JIALC and JIC instructions
This patch implements JIALC and JIC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8389

llvm-svn: 236748
2015-05-07 17:12:23 +00:00
Toma Tabacu 506cfd0b2b [mips] Add the SoftFloat MipsSubtarget feature.
Summary: This will enable the IAS to reject floating point instructions if soft-float is enabled.

Reviewers: dsanders, echristo

Reviewed By: dsanders

Subscribers: jfb, llvm-commits, mpf

Differential Revision: http://reviews.llvm.org/D9053

llvm-svn: 236713
2015-05-07 10:29:52 +00:00
Daniel Sanders 4160c802d9 [mips][msa] Test basic operations for the N32 ABI too.
Summary:
This required adding instruction aliases for dneg.

N64 will be enabled shortly but requires additional bugfixes.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9341

llvm-svn: 236489
2015-05-05 08:48:35 +00:00
Toma Tabacu 00e9867988 [mips] [IAS] Fix error messages for using LI with 64-bit immediates.
Summary:
LI should never accept immediates larger than 32 bits.
The additional Is32BitImm boolean also paves the way for unifying the functionality that LA and LI have in common.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9289

llvm-svn: 236313
2015-05-01 12:19:27 +00:00
Toma Tabacu a2861db834 [mips] [IAS] Slightly improve shift instruction generation in expandLoadImm.
Summary:
Generate one DSLL32 of 0 instead of two consecutive DSLL of 16.
In order to do this I had to change createLShiftOri's template argument from a bool to an unsigned.

This also gave me the opportunity to rewrite the mips64-expansions.s test, as it was testing the same cases multiple times and skipping over other cases.
It was also somewhat unreadable, as the CHECK lines were grouped in a huge block of text at the beginning of the file.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8974

llvm-svn: 236311
2015-05-01 10:26:47 +00:00
Daniel Sanders 811f21493c [mips][mips64r6] Sorted instructions in test. NFC.
llvm-svn: 236221
2015-04-30 10:23:48 +00:00
Zoran Jovanovic 387ce30685 [mips][microMIPSr6] Implement MUL, MUH, MULU and MUHU instructions
Differential Revision: http://reviews.llvm.org/D8894

llvm-svn: 236131
2015-04-29 17:23:22 +00:00
Zoran Jovanovic cca29e8f6e [mips][microMIPSr6] Implement SUB and SUBU instructions
Differential Revision: http://reviews.llvm.org/D8764

llvm-svn: 236118
2015-04-29 16:22:46 +00:00
Zoran Jovanovic 5f34d44354 [mips][microMIPSr6] Implement ADD, ADDU and ADDIU instructions
Differential Revision: http://reviews.llvm.org/D8704

llvm-svn: 236111
2015-04-29 15:11:07 +00:00
Toma Tabacu 7dea2e3982 [mips] [IAS] Do not generate redundant ORi in createLShiftOri.
Summary: If the immediate is 0, the ORi is pointless.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8969

llvm-svn: 235990
2015-04-28 14:06:35 +00:00
Rafael Espindola a7c3163cdf Use CIE version 1 for .eh_frame.
According to

http://www.linuxbase.org/betaspecs/lsb/LSB-Core-generic/LSB-Core-generic/ehframechpt.html

we should always use 1.

llvm-svn: 235923
2015-04-27 22:04:24 +00:00
Toma Tabacu d9d344b485 [mips] [IAS] Improve warning for using AT with .set noat.
Summary:
Changed the warning message to show the current value of $at, similar to what clang does for typedef's, and renamed warnIfAssemblerTemporary to a more descriptive name.

I also changed the type of variables which store registers from int to unsigned, updated the relevant test and tried to make the related comments clearer.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8479

llvm-svn: 235881
2015-04-27 14:05:04 +00:00
Toma Tabacu 11e14a9467 [mips] [IAS] Implement the .asciiz directive.
Summary:
This directive is exactly the same as .asciz, except it's only used by MIPS.
It is used to store null terminated strings in object files.

Reviewers: rafael, dsanders, echristo

Reviewed By: dsanders, echristo

Subscribers: echristo, llvm-commits

Differential Revision: http://reviews.llvm.org/D7530

llvm-svn: 235382
2015-04-21 11:50:52 +00:00
Jozef Kolek 8e086cedfa [mips][microMIPSr6] Implement CACHE and PREF instructions
Implement CACHE and PREF instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8893

llvm-svn: 235379
2015-04-21 11:17:25 +00:00
Jozef Kolek 207d248eba [mips][microMIPSr6] Implement BITSWAP instruction
Implement BITSWAP instruction using mapping.

Differential Revision: http://reviews.llvm.org/D8857

llvm-svn: 235321
2015-04-20 18:14:59 +00:00
Jozef Kolek 5de4a6c0af [mips][microMIPSr6] Implement BALC and BC instructions
This patch implements BALC and BC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8388

llvm-svn: 235302
2015-04-20 13:04:14 +00:00
Toma Tabacu 2cc44f50a5 [mips] [IAS] Preserve microMIPS label marking for objects when assigning.
Summary: Previously, this was only happening for functions, but because of .insn, objects can also be marked now.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8007

llvm-svn: 235095
2015-04-16 13:37:32 +00:00
Toma Tabacu 9ca5096f59 [mips] [IAS] Add support for the .insn directive.
Summary:
This assembler directive marks the current label as an instruction label in microMIPS and MIPS16.

This initial implementation works only for microMIPS.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8006

llvm-svn: 235084
2015-04-16 09:53:47 +00:00
Rafael Espindola 10f3de6889 Update tests to not be as dependent on section numbers.
Many of these predate llvm-readobj. With elf-dump we had to match
a relocation to symbol number and symbol number to symbol name or
section number.

llvm-svn: 235015
2015-04-15 15:59:37 +00:00
Petar Jovanovic 0380d0b88f Re-enable target-specific relocation table sorting and use it for Mips
Some targets (ie. Mips) have additional rules for ordering the relocation
table entries. Allow them to override generic sortRelocs(), which sorts
entries by Offset.
Then override this function for Mips, to emit HI16 and GOT16 relocations
against the local symbol in pair with the corresponding LO16 relocation.

Patch by Vladimir Stefanovic.

Differential Revision: http://reviews.llvm.org/D7414

llvm-svn: 234883
2015-04-14 13:23:34 +00:00
Toma Tabacu 038a330ede [mips] [IAS] Make the mips-expansions-bad.s test more readable. NFC.
Move the check lines below the code lines and change the indentation from 8
spaces to 2 spaces.

llvm-svn: 234584
2015-04-10 10:46:59 +00:00
Toma Tabacu c6ce0749ad [mips] [IAS] Do not generate redundant move when expanding lw/sw with symbol.
Summary:
Even though there is no 2nd register operand in the "lw/sw $8, symbol" case, we still try to find one, 
and we end up with $0, which makes us generate an unnecessary "addu $8, $8, $0" (a.k.a. "move $8, $8").

We can avoid this by checking if the 2nd register operand is different from $0, before generating the addu.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8055

llvm-svn: 234406
2015-04-08 13:52:41 +00:00
Toma Tabacu 91fc0b3c10 [mips] [IAS] Add support for the BNEZL and BEQZL pseudo-instructions.
Summary:
They are of the form "bnezl/beqzl $rs, offset" and expand to "bnel/beql $rs, $zero, offset".

These instructions are used in Linux inline assembly.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8540

llvm-svn: 234401
2015-04-08 12:15:05 +00:00
Toma Tabacu 7567a10c47 [mips] [IAS] Remove AssemblerPredicate's from RelocPIC and RelocStatic.
Summary:
These AssemblerPredicate's are unnecessary and actually make some instructions unusable when assembling pre-MIPS32 ISAs.
For example, this was causing the IAS to reject the 'j' instruction for MIPS I-V.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8300

llvm-svn: 234398
2015-04-08 10:06:45 +00:00
Toma Tabacu f25949b588 [mips] [IAS] Allow .set assignments for already defined symbols.
Summary:
This is not possible when using the IAS for MIPS, but it is possible when using the IAS for other architectures and when using GAS for MIPS.


Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8578

llvm-svn: 234316
2015-04-07 13:59:39 +00:00