5bde1cbd93
of -> or
...
llvm-svn: 85065
2009-10-25 19:14:48 +00:00
5a9788b979
80-column cleanup
...
llvm-svn: 85064
2009-10-25 18:55:46 +00:00
b18a46806b
Reapply 85006 with a minor fix.
...
llvm-svn: 85052
2009-10-25 08:14:11 +00:00
2e7dee5f23
Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing.
...
llvm-svn: 85049
2009-10-25 07:53:28 +00:00
5d1b849658
Don't forget subreg indices when folding load / store.
...
llvm-svn: 85048
2009-10-25 07:52:27 +00:00
974e12b2d3
Remove includes of Support/Compiler.h that are no longer needed after the
...
VISIBILITY_HIDDEN removal.
llvm-svn: 85043
2009-10-25 06:57:41 +00:00
02d5f77d26
Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
...
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
llvm-svn: 85042
2009-10-25 06:33:48 +00:00
13b8b56dd4
this is done.
...
llvm-svn: 85041
2009-10-25 06:17:51 +00:00
54d7179a25
Remove ICmpInst::isSignedPredicate which was a reimplementation
...
CmpInst::isSigned.
llvm-svn: 85037
2009-10-25 05:20:17 +00:00
9e8d42f295
Revert back 85006 for now as it breaks PIC16 tests.
...
llvm-svn: 85008
2009-10-24 18:19:41 +00:00
055c3305a1
Adding support for placing global objects in shared data memory.
...
llvm-svn: 85006
2009-10-24 18:02:44 +00:00
46ed1f8341
80 col violation.
...
llvm-svn: 84986
2009-10-24 02:07:42 +00:00
e2871d69db
Restrict Thumb1 register allocation to low registers, even for instructions that
...
can access the hi regs. Our prologue and epilogue code doesn't know how to
properly handle save/restore of the hi regs, so things go badly when we alloc
them.
llvm-svn: 84982
2009-10-24 00:19:24 +00:00
22b2c011f9
FIXME no longer applies. R12 and R3 are available for allocation
...
llvm-svn: 84977
2009-10-23 23:07:42 +00:00
851193b873
some stuff is done, we still have constantexpr simplification to do.
...
llvm-svn: 84943
2009-10-23 07:00:55 +00:00
8b86efefec
X86 needs critical path anti-dependency breaking.
...
llvm-svn: 84931
2009-10-23 05:57:35 +00:00
02ad4cb32e
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
...
llvm-svn: 84911
2009-10-22 23:19:17 +00:00
9d763cc3f8
Revert 84843. Evan, this was breaking some of the if-conversion tests.
...
llvm-svn: 84868
2009-10-22 16:52:21 +00:00
c77f8634e5
Shift art to the right to keep GCC from complaining about multi-line comments.
...
llvm-svn: 84849
2009-10-22 09:28:49 +00:00
3615b9bef3
Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly.
...
llvm-svn: 84843
2009-10-22 06:48:32 +00:00
943f4f41f2
Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit.
...
llvm-svn: 84842
2009-10-22 06:47:35 +00:00
5457a96b63
Trim more includes.
...
llvm-svn: 84832
2009-10-22 05:11:00 +00:00
344fcd9d61
Trim include.
...
llvm-svn: 84831
2009-10-22 05:08:49 +00:00
1448799377
fix warning.
...
llvm-svn: 84826
2009-10-22 03:42:27 +00:00
0f55e9ce2e
Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.
...
llvm-svn: 84813
2009-10-22 00:40:00 +00:00
f1ad2c618a
Use special DAG-to-DAG preprocessing to allow mem-mem instructions to be selected.
...
Yay for ASCII graphics!
llvm-svn: 84808
2009-10-22 00:16:00 +00:00
f2e74df12e
Missing piece of the ARM frame index post-scavenging conditionalization
...
llvm-svn: 84798
2009-10-21 23:40:56 +00:00
05536f50dc
Conditionalize ARM/T2 frame index post-scavenging while working out fixes
...
for a few bugs.
llvm-svn: 84791
2009-10-21 22:59:24 +00:00
854530a7dd
Most of the NEON shuffle instructions do not support 64-bit element types.
...
llvm-svn: 84785
2009-10-21 21:36:27 +00:00
b45d621ab1
Revert r84764, it breaks mingw build
...
llvm-svn: 84783
2009-10-21 21:15:18 +00:00
a93ca3c637
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
...
immediate operands when they will fit into the using instruction.
llvm-svn: 84778
2009-10-21 20:44:34 +00:00
9e92857b38
Add DAG printing for RMW stuff debugging
...
llvm-svn: 84776
2009-10-21 19:18:28 +00:00
ccfa3e31f7
RMW preprocessing stuff was incorrect. Grab the stuff from x86 backend and disable some tests until it will be clever enough to handle them.
...
llvm-svn: 84775
2009-10-21 19:17:55 +00:00
5399c2d05e
Implement branch folding
...
llvm-svn: 84774
2009-10-21 19:17:18 +00:00
2983dcb1f2
Cosmetic changes, no functionality changes
...
llvm-svn: 84773
2009-10-21 19:16:49 +00:00
0db964a3a0
Fix NEON VST2LN instruction encoding.
...
Patch by Johnny Chen.
llvm-svn: 84767
2009-10-21 17:54:01 +00:00
87671da29a
Revert 84732. It was the wrong fix.
...
llvm-svn: 84766
2009-10-21 17:52:34 +00:00
c5804f3cb6
Build shared lib instead of an archive.
...
llvm-svn: 84764
2009-10-21 17:27:23 +00:00
47ea743618
Add a pass to overlay pic16 data sections for function frame and automatic
...
variables. This pass can be invoked by llvm-ld or opt to traverse over the call graph
to detect what function frames and their automatic variables can be overlaid.
Currently this builds an archive , but needs to be changed to a loadable module.
llvm-svn: 84753
2009-10-21 10:42:44 +00:00
786b15fe12
Match more patterns to movt.
...
llvm-svn: 84751
2009-10-21 08:15:52 +00:00
175d04c90f
tidy
...
llvm-svn: 84738
2009-10-21 04:10:24 +00:00
5b5cb92816
Fix some more NEON instruction encoding problems.
...
Thanks to Johnny Chen for discovering the problem.
llvm-svn: 84732
2009-10-21 02:27:20 +00:00
bd3650cc84
Leave some NEON instruction encoding bits unspecified instead of setting
...
a default value of zero. This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.
llvm-svn: 84730
2009-10-21 02:15:46 +00:00
bc69313909
IPSCCP is missing stuff.
...
llvm-svn: 84725
2009-10-21 01:10:37 +00:00
7099d0c19c
Add note
...
llvm-svn: 84713
2009-10-21 00:14:15 +00:00
e43af4a085
Be crazy and assert in case of unsupported modifier passed.
...
llvm-svn: 84712
2009-10-21 00:13:58 +00:00
11074fa73e
Handle external symbols
...
llvm-svn: 84711
2009-10-21 00:13:42 +00:00
cc55b9086d
Distinguish between pcrel imm operands and 'normal' ones. Fix fixes gross weirdness of asmprinting.
...
llvm-svn: 84710
2009-10-21 00:13:25 +00:00
94ba9c27b0
Add basic block operands & jump kinds
...
llvm-svn: 84709
2009-10-21 00:13:05 +00:00
8a06a4e5c8
Ignore all implicit reg operands
...
llvm-svn: 84708
2009-10-21 00:12:44 +00:00
196b0e5431
Add a workaround for different memops prefixes
...
llvm-svn: 84707
2009-10-21 00:12:27 +00:00
4e32bff382
Checkpoint MCInst printer. We (almostly) able to print global / JT / constpool entries
...
llvm-svn: 84706
2009-10-21 00:12:08 +00:00
7fbc0a50d5
Add simple operand printing stuff
...
llvm-svn: 84704
2009-10-21 00:11:27 +00:00
6e78029d82
Add experimental MSP430 MCInstLowering stuff
...
llvm-svn: 84703
2009-10-21 00:11:08 +00:00
daaa2f0c31
Wire up MSP430 printMCInst() method
...
llvm-svn: 84702
2009-10-21 00:10:47 +00:00
b6e2e4fd50
Add MSP430 InstPrinter stub
...
llvm-svn: 84701
2009-10-21 00:10:30 +00:00
13de81ac40
Use proper target data
...
llvm-svn: 84700
2009-10-21 00:10:00 +00:00
a470eac6a1
Fix -Asserts warning.
...
llvm-svn: 84687
2009-10-20 22:10:05 +00:00
cccf5084a3
Disable by default while debugging
...
llvm-svn: 84669
2009-10-20 20:31:31 +00:00
f3a2b6499e
add cmd line opt to disable frame index reuse for ARM and T2. debug aid.
...
llvm-svn: 84664
2009-10-20 20:19:50 +00:00
3d9d78463c
Following r84485, add Defs = [EFLAGS] to the 32-bit lock instructions too.
...
llvm-svn: 84652
2009-10-20 18:14:49 +00:00
4a43e3068d
Make TranslateX86CC return COND_INVALID instead of aborting when it
...
encounters an OEQ or UNE comparison, and update its callers to check
for this return status and recover. This fixes a problem resulting from
the LowerOperation hooks being called from LegalizeVectorOps, because
LegalizeVectorOps only lowers vectors, so OEQ and UNE comparisons may
still be at large. This fixes PR5092.
llvm-svn: 84640
2009-10-20 16:22:37 +00:00
3301207a15
Random #include pruning.
...
llvm-svn: 84632
2009-10-20 11:44:38 +00:00
8296e62244
This file is replaeced by PIC16Section.h.
...
llvm-svn: 84628
2009-10-20 09:16:32 +00:00
9351e4f4b2
implement some more easy hooks.
...
llvm-svn: 84614
2009-10-20 06:22:33 +00:00
60d5131653
Implement some hooks, make printOperand abort if unknown modifiers are
...
present.
llvm-svn: 84613
2009-10-20 06:15:28 +00:00
227767b4e5
t2MOVi32imm is currently always lowered by the Thumb2ITBlockPass.
...
llvm-svn: 84611
2009-10-20 05:58:02 +00:00
f0b3d15cfe
Wire up the ARM MCInst printer, for llvm-mc.
...
llvm-svn: 84600
2009-10-20 05:15:36 +00:00
34f040a575
Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*
...
functions are not needed.
llvm-svn: 84587
2009-10-20 01:32:47 +00:00
84f6235b6f
Enable post-pass frame index register scavenging for ARM and Thumb2
...
llvm-svn: 84585
2009-10-20 01:26:58 +00:00
484d2e9491
lower ARM::MOVi32imm properly.
...
llvm-svn: 84583
2009-10-20 01:11:37 +00:00
43c5589a7e
add support for external symbols. The mc instprinter can now handle
...
reasonable code like Codegen/ARM/2009-02-27-SpillerBug.ll, producing
identical output except for superior formatting of constant pool entries.
llvm-svn: 84582
2009-10-20 00:56:16 +00:00
1b06acbd70
get fancy: support basic block operands. Yay for jumps.
...
llvm-svn: 84579
2009-10-20 00:52:47 +00:00
85ab670644
add supprort for the 'sbit' operand, MOVi apparently has one.
...
llvm-svn: 84577
2009-10-20 00:46:11 +00:00
19c52201bd
add support for instruction predicates.
...
llvm-svn: 84575
2009-10-20 00:42:49 +00:00
2f69ed8f4c
implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :)
...
llvm-svn: 84573
2009-10-20 00:40:56 +00:00
772b2f84eb
Refs: A8-598.
...
Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.
Patch by Johnny Chen.
llvm-svn: 84572
2009-10-20 00:38:19 +00:00
68f495caad
Add missing encoding bits to NLdSt class of instructions.
...
Patch by Johnny Chen.
llvm-svn: 84570
2009-10-20 00:19:08 +00:00
0b4a59fc07
X86 should ignore implicit regs when lowering to MCInst also,
...
no functionality change.
llvm-svn: 84567
2009-10-19 23:35:57 +00:00
bd531262f8
handle addmode4 modifiers, fix a fixme in printRegisterList
...
by ignoring all implicit regs when lowering.
llvm-svn: 84566
2009-10-19 23:31:43 +00:00
d99b6974b9
simplify by using the twine form of GetOrCreateSymbol
...
llvm-svn: 84565
2009-10-19 23:05:23 +00:00
f5f263f1b4
Enable allocation of R3 in Thumb1
...
llvm-svn: 84563
2009-10-19 22:57:03 +00:00
d91c11091d
use EmitLabel instead of text emission
...
llvm-svn: 84562
2009-10-19 22:51:16 +00:00
86dfd73c38
add a twine version of MCContext::GetOrCreateSymbol.
...
llvm-svn: 84561
2009-10-19 22:49:00 +00:00
186c6b0834
lower the ARM::CONSTPOOL_ENTRY pseudo op, giving us constant pool entries
...
like:
@ BB#1:
.align 2
LCPI1_0:
.long L_.str-(LPC0+8)
Note that proper indentation of the label :)
llvm-svn: 84558
2009-10-19 22:33:05 +00:00
5a5a3bc5d4
Adjust the scavenge register spilling to allow the target to choose an
...
appropriate restore location for the spill as well as perform the actual
save and restore.
The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.
llvm-svn: 84554
2009-10-19 22:27:30 +00:00
add5749ac8
add MCInstLower support for lowering ARM::PICADD, a pseudo op for pic stuffola.
...
llvm-svn: 84553
2009-10-19 22:23:04 +00:00
ef2979b1da
add register list and hacked up addrmode #4 support, we now get this:
...
_main:
stmsp! sp!, {r7, lr}
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0, [sp]
ldr r0, LCPI1_0
bl _printf
ldr r0, [sp]
mov sp, r7
ldmsp! sp!, {r7, pc}
Note the unhappy ldm/stm because of modifiers being ignored.
llvm-svn: 84546
2009-10-19 22:09:23 +00:00
f264f8a21c
revert r84540, fixing build breakage I didn't see because of
...
broken makefile deps :(
llvm-svn: 84544
2009-10-19 21:59:25 +00:00
7ddfdc4133
add addrmode2 support, getting us up to:
...
_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0, [sp]
ldr r0, LCPI1_0
bl _printf
ldr r0, [sp]
mov sp, r7
ldm ,
llvm-svn: 84543
2009-10-19 21:57:05 +00:00
889a6217fa
add jump tables, constant pools and some trivial global
...
lowering stuff. We can now compile hello world to:
_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0,
ldr r0,
bl _printf
ldr r0,
mov sp, r7
ldm ,
Almost looks like arm code :)
llvm-svn: 84542
2009-10-19 21:53:00 +00:00
e3796a0fee
pass mangler in as a reference instead of a pointer.
...
llvm-svn: 84540
2009-10-19 21:45:31 +00:00
8bd9b9d3fa
reduce #includes
...
llvm-svn: 84536
2009-10-19 21:23:15 +00:00
89d47205b5
add printing support for SOImm operands, getting us to:
...
_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0,
llvm-svn: 84535
2009-10-19 21:21:39 +00:00
93e3ef6536
wire up some basic printOperand goodness, giving us stuff like this before
...
we abort:
_main:
stm ,
mov r7, sp
sub sp, sp,
mov r0,
str r0,
llvm-svn: 84532
2009-10-19 20:59:55 +00:00
78393d79a0
add the files that go with the previous rev
...
llvm-svn: 84531
2009-10-19 20:21:05 +00:00
71eb077c15
wire up skeletal support for having llc print instructions
...
through mcinst lowering -> mcinstprinter, when llc is passed
the -enable-arm-mcinst-printer flag. Currently this
is very "aborty".
llvm-svn: 84530
2009-10-19 20:20:46 +00:00
296544e15f
wire up ARM's printMCInst method. Now llvm-mc should be able to produce
...
"something" when printing MCInsts, it will just be missing all the
operand info.
llvm-svn: 84528
2009-10-19 19:59:05 +00:00
a290778859
stub out a minimal ARMInstPrinter.
...
llvm-svn: 84527
2009-10-19 19:56:26 +00:00
5db7b6a5d4
remove strings from instructions who are never asmprinted.
...
All of these "subreg32" modifier instructions are handled
explicitly by the MCInst lowering phase. If they got to
the asmprinter, they would explode. They should eventually
be replace with correct use of subregs.
llvm-svn: 84526
2009-10-19 19:51:42 +00:00
8d2e3a28d6
simplify code, reducing string thrashing.
...
llvm-svn: 84521
2009-10-19 18:49:14 +00:00
3334deb19b
switch hidden gv stubs to use MachineModuleInfoMachO instead of a custom map.
...
llvm-svn: 84520
2009-10-19 18:44:38 +00:00
6462adcd20
use MachineModuleInfoMachO for non-lazy gv stubs instead of a private map.
...
llvm-svn: 84519
2009-10-19 18:38:33 +00:00
24fcb826bd
remove dead map
...
llvm-svn: 84513
2009-10-19 18:11:25 +00:00
84a493ca21
don't bother trying to avoid emitting redundant constant pool alignment directives.
...
llvm-svn: 84512
2009-10-19 18:08:02 +00:00
66ebfab3ab
remove accidental comment.
...
llvm-svn: 84510
2009-10-19 18:03:41 +00:00
e6da1826e8
emit .subsections_via_symbols through MCStreamer instead of textually.
...
llvm-svn: 84509
2009-10-19 18:03:08 +00:00
ee9399acaa
cleanup doFinalization -> EmitEndOfAsmFile.
...
llvm-svn: 84508
2009-10-19 17:59:19 +00:00
5ca7b345b9
PR 5245 - The imediate size target flag was not set on 3A-prefixed SSSE3 instructions.
...
llvm-svn: 84506
2009-10-19 17:31:16 +00:00
033f01c922
Fix PR5247, "lock addq" pattern (and other atomics), it DOES modify EFLAGS.
...
LLC was scheduling compares before the adds causing wrong branches to be taken
in programs, resulting in misoptimized code wherever atomic adds where used.
llvm-svn: 84485
2009-10-19 11:00:58 +00:00
18df82a20c
Add support for matching shuffle patterns with palignr.
...
llvm-svn: 84459
2009-10-19 02:17:23 +00:00
c436631a9c
Turn on post-alloc scheduling for x86.
...
llvm-svn: 84431
2009-10-18 19:57:27 +00:00
936d87b39d
Oops. I forgot to change the tests first. Disable post-alloc scheduling.
...
llvm-svn: 84425
2009-10-18 18:31:31 +00:00
0e9d9ca855
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
...
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2 .
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
llvm-svn: 84424
2009-10-18 18:16:27 +00:00
0b8db2dab7
Only fixed stack objects and spill slots should be get FixedStack PseudoSourceValue.
...
llvm-svn: 84411
2009-10-18 06:27:36 +00:00
4729191bb2
Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues.
...
llvm-svn: 84326
2009-10-17 09:20:14 +00:00
8759585aba
Revert 84315 for now. Re-thinking the patch.
...
llvm-svn: 84321
2009-10-17 07:53:04 +00:00
0818d87ed1
Rename getFixedStack to getStackObject. The stack objects represented are not
...
necessarily fixed. Only those will negative frame indices are "fixed."
llvm-svn: 84315
2009-10-17 06:22:26 +00:00
a3aaf85e23
Remove MallocInst from LLVM Instructions.
...
llvm-svn: 84299
2009-10-17 01:18:07 +00:00
007ceb4603
Change createPostRAScheduler so it can be turned off at llc -O1.
...
llvm-svn: 84273
2009-10-16 21:06:15 +00:00
ca019e704c
Update CMake file.
...
llvm-svn: 84252
2009-10-16 10:29:08 +00:00
89259d7929
Cleaned up some code. No functionality change.
...
llvm-svn: 84251
2009-10-16 08:58:34 +00:00
343d17d762
I am no spelling bee.
...
llvm-svn: 84250
2009-10-16 06:18:09 +00:00
03da4dba59
Enable post-alloc scheduling for all ARM variants except for Thumb1.
...
llvm-svn: 84249
2009-10-16 06:11:08 +00:00
8cd7c92613
Add comment.
...
llvm-svn: 84246
2009-10-16 05:33:58 +00:00
01404ecec7
Fix more NEON instruction encodings.
...
Patch by Johnny Chen.
llvm-svn: 84243
2009-10-16 03:58:44 +00:00
419160bd79
Revert svn r80498 and replace it with a different solution. The only problem
...
I can see with the original code was that I forgot that this runs after
type legalization and hence the result type will always be i32. (Custom
legalization of EXTRACT_VECTOR_ELT is only enabled for vector types with
8- and 16-bit elements.)
Regarding the FIXME comment: any information about sign and zero-extension
should be captured by separate extension operations. The DAG combiner should
handle those to produce either VGETLANEu or VGETLANEs, and that seems to be
working now. If there are cases that we're missing, let me know.
llvm-svn: 84218
2009-10-15 23:12:05 +00:00
49e417c52c
Dllexport stuff cleanup:
...
1. Emit external function type information for all COFF targets since it's
a feature of object format
2. Emit linker directives only for cygming (since this is ld-specific stuff)
llvm-svn: 84214
2009-10-15 22:36:18 +00:00
3f23601b00
Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng.
...
llvm-svn: 84212
2009-10-15 22:25:32 +00:00
4138b11c93
Fix encoding bits for N3VLInt3_QHS multiclass with 8-bit elements.
...
Patch by Johnny Chen.
llvm-svn: 84206
2009-10-15 21:57:47 +00:00
644de27659
Fix ARM memory operand parsing of post indexing with just a base register, that
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is just "[Rn]" and no tailing comma with an offset, etc.
llvm-svn: 84205
2009-10-15 21:42:45 +00:00
2f9be50774
Fix a potential performance problem in placing ARM constant pools.
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In the case where there are no good places to put constants and we fall back
upon inserting unconditional branches to make new blocks, allow all constant
pool references in range of those blocks to put constants there, even if that
means resetting the "high water marks" for those references. This will still
terminate because you can't keep splitting blocks forever, and in the bad
cases where we have to split blocks, it is important to avoid splitting more
than necessary.
llvm-svn: 84202
2009-10-15 20:49:47 +00:00
146dcf2ab5
More bits of the ARM target assembler for llvm-mc, code added to parse labels
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as expressions, code for parsing a few arm specific directives (still needs
the MCStreamer calls for these). Some clean up of the operand parsing code
and adding some comments.
llvm-svn: 84201
2009-10-15 20:48:48 +00:00
e4a2117161
Remove X86Subtarget::IsLinux. It's no longer being used.
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llvm-svn: 84200
2009-10-15 20:23:21 +00:00
74c35c126a
Add files Sanjiv forgot.
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llvm-svn: 84196
2009-10-15 19:46:34 +00:00
a07cae65e3
Re-apply 84180 with the fixed test case.
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llvm-svn: 84195
2009-10-15 19:26:25 +00:00
460ceae432
Move Blackfin intrinsics into the Target/Blackfin directory.
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llvm-svn: 84194
2009-10-15 18:50:52 +00:00
923b5aa973
Clean up TargetIntrinsicInfo API. Add pure virtual methods.
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llvm-svn: 84192
2009-10-15 18:49:26 +00:00
3b5bdd536b
Revert "Complete Rewrite of AsmPrinter, TargetObjectFile based on new
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PIC16Section class", it breaks globals.ll.
llvm-svn: 84184
2009-10-15 15:02:14 +00:00
917db86b42
Complete Rewrite of AsmPrinter, TargetObjectFile based on new PIC16Section class
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derived from MCSection.
llvm-svn: 84180
2009-10-15 10:10:43 +00:00
7357636091
Few changes to comply with new DebugInfo Metadata representation.
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llvm-svn: 84179
2009-10-15 09:48:25 +00:00
68ead6c7a8
Be smarter about reusing constant pool entries.
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llvm-svn: 84173
2009-10-15 05:52:29 +00:00
b4f2a85fe4
Fix another problem with ARM constant pools. Radar 7303551.
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When ARMConstantIslandPass cannot find any good locations (i.e., "water") to
place constants, it falls back to inserting unconditional branches to make a
place to put them. My recent change exposed a problem in this area. We may
sometimes append to the same block more than one unconditional branch. The
symptoms of this are that the generated assembly has a branch to an undefined
label and running llc with -debug will cause a seg fault.
This happens more easily since my change to prevent CPEs from moving from
lower to higher addresses as the algorithm iterates, but it could have
happened before. The end of the block may be in range for various constant
pool references, but the insertion point for new CPEs is not right at the end
of the block -- it is at the end of the CPEs that have already been placed
at the end of the block. The insertion point could be out of range. When
that happens, the fallback code will always append another unconditional
branch if the end of the block is in range.
The fix is to only append an unconditional branch if the block does not
already end with one. I also removed a check to see if the constant pool load
instruction is at the end of the block, since that is redundant with
checking if the end of the block is in-range.
There is more to be done here, but I think this fixes the immediate problem.
llvm-svn: 84172
2009-10-15 05:10:36 +00:00
cfcf6bc70d
Fix instruction encoding bits for NEON VPADAL.
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Patch by Johnny Chen.
llvm-svn: 84146
2009-10-14 21:43:17 +00:00
ad03cf02f6
Remove unused variables to fix build warning.
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llvm-svn: 84144
2009-10-14 21:40:45 +00:00
94068707e1
Inst{11-8} for vshl should be 0b0101, not 0b1111.
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Refs: A7-17 & A8-750.
Patch by Johnny Chen.
llvm-svn: 84131
2009-10-14 20:31:01 +00:00
1a791eedbf
Set instruction encoding bits 4 and 7 for ARM register-register and
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register-shifted-register instructions. Patch by Johnny Chen.
llvm-svn: 84124
2009-10-14 19:00:24 +00:00
c350cdf3b3
Refactor code to select NEON VST intrinsics.
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llvm-svn: 84122
2009-10-14 18:32:29 +00:00
12b4799787
Refactor code to select NEON VLD intrinsics.
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llvm-svn: 84117
2009-10-14 17:28:52 +00:00
93117bc499
More refactoring. NEON vst lane intrinsics can share almost all the code for
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vld lane intrinsics.
llvm-svn: 84110
2009-10-14 16:46:45 +00:00
Jim Grosbach