Commit Graph

3042 Commits

Author SHA1 Message Date
Zoran Jovanovic 507e084a18 Support for microMIPS jump instructions
llvm-svn: 193623
2013-10-29 16:38:59 +00:00
Bernard Ogden fce246f0c6 Test cleanup for v8 instructions
Add some missing tests, factor out a test not specific to v8 into
its own file.

llvm-svn: 193611
2013-10-29 14:16:09 +00:00
Bernard Ogden ee87e85505 ARM: Add subtarget feature for CRC
Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend.

Differential Revision: http://llvm-reviews.chandlerc.com/D2036

llvm-svn: 193599
2013-10-29 09:47:35 +00:00
Joerg Sonnenberger fc18473400 Move the STT_FILE symbols out of the normal symbol table processing for
ELF. They can overlap with the other symbols, e.g. if a source file
"foo.c" contains a function "foo" with a static variable "c".

llvm-svn: 193569
2013-10-29 01:06:17 +00:00
Rafael Espindola d1cac0af6b Convert another llc -filetype=obj test.
llvm-svn: 193548
2013-10-28 22:17:19 +00:00
Rafael Espindola 3a8c0734f9 Convert another llc -filetype=obj test.
llvm-svn: 193547
2013-10-28 22:11:47 +00:00
Rafael Espindola 060e6444ea Convert another llc -filetype=obj test.
llvm-svn: 193546
2013-10-28 22:05:05 +00:00
Rafael Espindola 940ca0bada Convert another llc -filetype=obj test.
llvm-svn: 193539
2013-10-28 21:12:15 +00:00
Rafael Espindola 57ec995c37 Convert another llc -filetype=obj test.
llvm-svn: 193538
2013-10-28 21:06:12 +00:00
Rafael Espindola 3a5eecb57c Convert another llc -filetype=obj test.
llvm-svn: 193537
2013-10-28 20:59:41 +00:00
Rafael Espindola 3f018baac0 Convert another llc -filetype=obj test.
llvm-svn: 193536
2013-10-28 20:54:33 +00:00
Lang Hames b52816615b Return early from getUnconditionalBranchTargetOpValue if the branch target is
an MCExpr, in order to avoid writing an encoded zero value in the immediate
field.

When getUnconditionalBranchTargetOpValue is called with an MCExpr target, we
don't know what the final immediate field value should be. We shouldn't
explicitly set the immediate field to an encoded zero value as zero is encoded
with a non-zero bit pattern. This leads to bits being set that pollute the
final immediate value. The nature of the encoding is such that the polluted
bits only affect very large immediate values, explaining why this hasn't
caused problems earlier.

Fixes <rdar://problem/15155975>.

llvm-svn: 193535
2013-10-28 20:51:11 +00:00
Rafael Espindola 889a180e5a Convert a llc -filetype=obj test into a llvm-mc test.
llvm-svn: 193534
2013-10-28 20:40:20 +00:00
Logan Chien 8cbb80d159 [arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.

To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.

Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.

This commit changes the test cases:

* Several .eabi_attribute directives in
  2010-09-29-mc-asm-header-test.ll are removed because the .fpu
  directive already cover the functionality.

* In the Cortex-A15 test case, the value for
  Tag_Advanced_SIMD_arch has be changed from 1 to 2,
  which is more precise.

llvm-svn: 193524
2013-10-28 17:51:12 +00:00
Tim Northover 1744d0ad83 ARM: allow .thumb_func to be separated from symbol definition
When assembling, a .thumb_func directive is supposed to be applicable to the
next symbol definition, even if there are intervening directives. We were
racing ahead to try and find it, and this commit should fix the issue.

Patch by Gabor Ballabas

llvm-svn: 193403
2013-10-25 12:49:50 +00:00
Tim Northover 41d2049180 ARM: tweak test to pass on all platforms
A TableGen indeterminacy means that the reason for the failure can
vary, and Windows gets the other option.

llvm-svn: 193394
2013-10-25 07:34:56 +00:00
Tim Northover 5620faf771 ARM: Mark double-precision instructions as such
This prevents us from silently accepting invalid instructions on (for example)
Cortex-M4 with just single-precision VFP support.

No tests for the extra Pat Requires because they're essentially assertions: the
affected code should have been lowered to libcalls before ISel.

rdar://problem/15302004

llvm-svn: 193354
2013-10-24 15:49:39 +00:00
Tim Northover 225bcbbe71 ARM: add a couple more NEON predicates.
The fused multiply instructions were added in VFPv4 but are still NEON
instructions, in particular they shouldn't be available on a Cortex-M4 not
matter how floaty it is.

llvm-svn: 193342
2013-10-24 12:48:05 +00:00
Tim Northover 64dacb2b8a ARM: mark various aliases with their architecture requirements.
If an alias inherits directly from InstAlias then it doesn't get any default
"Requires" values, so llvm-mc will allow it even on architectures that don't
support the underlying instruction.

This tidies up the obvious VFP and NEON cases I found.

llvm-svn: 193340
2013-10-24 12:22:58 +00:00
Zoran Jovanovic 2f0a712e18 Added tests for microMIPS relocations 1.
llvm-svn: 193332
2013-10-24 10:55:00 +00:00
Tim Northover 741e6ef4d4 ARM: fix assert on unpredictable POP instruction.
POP instructions are aliased to the ARM LDM variants but have different syntax.
This caused two problems: we tried to access a non-existent operand to annotate
the '!', and the error message didn't make much sense.

With some vigorous hand-waving in the error message both problems can be
fixed.

llvm-svn: 193322
2013-10-24 09:37:18 +00:00
Matheus Almeida be8681b461 [mips][msa] Direct Object Emission support for the LSA instruction.
llvm-svn: 193240
2013-10-23 13:20:07 +00:00
Artyom Skrobov fc12e7016c Make ARM hint ranges consistent, and add tests for these ranges
llvm-svn: 193238
2013-10-23 10:14:40 +00:00
David Blaikie 15b25dffc3 MC: Support multiple sections with the same name in the same comdat group
Code review by Eric Christopher and Rafael Espindola.

llvm-svn: 193209
2013-10-22 23:41:52 +00:00
Tim Northover 08a8660260 ARM: provide diagnostics on more writeback LDM/STM instructions
The set of circumstances where the writeback register is allowed to be in the
list of registers is rather baroque, but I think this implements them all on
the assembly parsing side.

For disassembly, we still warn about an ARM-mode LDM even if the architecture
revision is < v7 (the required architecture information isn't available). It's
a silly instruction anyway, so hopefully no-one will mind.

rdar://problem/15223374

llvm-svn: 193185
2013-10-22 19:00:39 +00:00
Matheus Almeida eb68d9d985 [mips][msa] Direct Object Emission support for conditional branches.
These branches have a 16-bit offset (R_MIPS_PC16).

List of conditional branch instructions:
bnz.{b,h,w,d}
bnz.v
bz.{b,h,w,d}
bz.v

llvm-svn: 193157
2013-10-22 09:43:32 +00:00
Matheus Almeida fe0bf9f618 [mips][msa] Direct Object Emission support for LD/ST instructions.
llvm-svn: 193082
2013-10-21 13:07:13 +00:00
Matheus Almeida 8ddad15177 [mips][msa] Direct Object Emission support for LDI instructions.
llvm-svn: 193081
2013-10-21 12:56:20 +00:00
Matheus Almeida 83d797de4a [mips][msa] Direct Object Emission support for MOVE.v.
llvm-svn: 193080
2013-10-21 12:43:54 +00:00
Matheus Almeida a591fdc63c [mips][msa] Direct Object Emission support for CTCMSA and CFCMSA.
These instructions are logically related as they allow read/write of MSA control registers.
Currently MSA control registers are emitted by number but hopefully that will change as soon 
as GAS starts accepting them by name as that would make the assembly easier to read.

llvm-svn: 193078
2013-10-21 12:26:50 +00:00
Matheus Almeida 5798c6f3bb [mips][msa] Direct Object Emission of SPLAT instruction.
llvm-svn: 193077
2013-10-21 12:07:26 +00:00
Matheus Almeida 70fbf77546 [mips][msa] Fix definition of SLD instruction.
The second parameter of the SLD intrinsic is the number of columns (GPR) to 
slide left the source array.

llvm-svn: 193076
2013-10-21 11:47:56 +00:00
Peter Collingbourne 588009e484 Emit DWARF line entries for all data in the instruction stream.
r182712 attempted to do this, but it failed to handle data emitted via
EmitBytes.

llvm-svn: 193041
2013-10-20 02:16:18 +00:00
Hans Wennborg ce69d77cec MC asm parser: allow ?'s in symbol names, and handle @'s in names in MS asm
This is another (final?) stab at making us able to parse our own asm output
on Windows.

Symbols on Windows often contain @'s and ?'s in their names. Our asm parser
didn't like this. ?'s were not allowed, and @'s were intepreted as trying to
reference PLT/GOT/etc.

We can't just add quotes around the bad names, since e.g. for MinGW, we use gas
to assemble, and it doesn't like quotes in some places (notably in .def
directives).

This commit makes us allow ?'s in symbol names, and @'s in symbol names for MS
assembly.

Differential Revision: http://llvm-reviews.chandlerc.com/D1978

llvm-svn: 193000
2013-10-18 20:46:28 +00:00
Richard Barton 87dacc38b8 Add hint disassembly syntax for 16-bit Thumb hint instructions.
Patch by Artyom Skrobov

llvm-svn: 192972
2013-10-18 14:09:49 +00:00
Chad Rosier fe2f58c8a1 [AArch64] Add support for NEON scalar extract narrow instructions.
llvm-svn: 192970
2013-10-18 14:03:24 +00:00
Silviu Baranga 314e58fdcc Add hardware division as a default feature on Cortex-A15. Also add test cases to check this, and change diagnostics for the hwdiv-arm feature to something useful.
llvm-svn: 192963
2013-10-18 10:18:40 +00:00
Hans Wennborg 7ddcdc82a5 Revert "Re-commit r192758 - MC: quote tricky symbol names in asm output"
This caused the clang-native-mingw32-win7 buildbot to break.

The assembler was complaining about the following lines that were showing up
in the asm for CrashRecoveryContext.cpp:

  movl  $"__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4", 4(%eax)
  calll "_AddVectoredExceptionHandler@8"
  .def   "__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4";
  "__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4":
  calll "_RemoveVectoredExceptionHandler@4"

Reverting for now.

llvm-svn: 192940
2013-10-18 02:14:40 +00:00
Chad Rosier 37d29173aa [AArch64] Add support for NEON scalar three register different instruction
class.  The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.

llvm-svn: 192908
2013-10-17 18:12:29 +00:00
Hans Wennborg 69918bccab Re-commit r192758 - MC: quote tricky symbol names in asm output
The reason this got reverted was that the @feat.00 symbol which was emitted
for every TU became quoted, and on cygwin/mingw we use the gas assembler which
couldn't handle the quotes.

This commit fixes the problem by only emitting @feat.00 for win32, where we use
clang -cc1as to assemble. gas would just drop this symbol anyway, so there is no
loss there.

With @feat.00 gone, there shouldn't be quoted symbols showing up on cygwin since
it uses the Itanium ABI, which doesn't put these funny characters in symbols.

> Because of win32 mangling, we produce symbol and section names with
> funny characters in them, most notably @ characters.
>
> MC would choke on trying to parse its own assembly output. This patch addresses
> that by:
>
> - Making @ trigger quoting of symbol names
> - Also quote section names in the same way
> - Just parse section names like other identifiers (to allow for quotes)
> - Don't assume @ signifies a symbol variant if it is in a string.

llvm-svn: 192859
2013-10-17 01:13:02 +00:00
Chad Rosier 846a72539c [AArch64] Add support for NEON scalar negate instruction.
llvm-svn: 192843
2013-10-16 21:04:39 +00:00
Chad Rosier 175601d997 [AArch64] Add support for NEON scalar absolute value instruction.
llvm-svn: 192842
2013-10-16 21:04:34 +00:00
Chad Rosier abe458d0bf Update comment.
llvm-svn: 192806
2013-10-16 16:30:10 +00:00
Chad Rosier 178b1cefc7 [AArch64] Add support for NEON scalar signed saturating accumulated of unsigned
value and unsigned saturating accumulate of signed value instructions.

llvm-svn: 192800
2013-10-16 16:09:02 +00:00
NAKAMURA Takumi 272416fda9 Revert r192758 (and r192759), "MC: Better handling of tricky symbol and section names"
GNU AS didn't like quotes in symbol names.

    Error: junk at end of line, first unrecognized character is `"'

        .def "@feat.00";
        "@feat.00" = 1

Reproduced on Cygwin's 2.23.52.20130309 and mingw32's 2.20.1.20100303.

llvm-svn: 192775
2013-10-16 08:22:49 +00:00
Hans Wennborg 6468493250 dos2unix on quoted-names.ll
llvm-svn: 192759
2013-10-16 01:22:07 +00:00
Hans Wennborg d34cf14339 MC: Better handling of tricky symbol and section names
Because of win32 mangling, we produce symbol and section names with
funny characters in them, most notably @ characters.

MC would choke on trying to parse its own assembly output. This patch addresses
that by:

- Making @ trigger quoting of symbol names
- Also quote section names in the same way
- Just parse section names like other identifiers (to allow for quotes)
- Don't assume @ signifies a symbol variant if it is in a string.

Differential Revision: http://llvm-reviews.chandlerc.com/D1945

llvm-svn: 192758
2013-10-16 01:20:40 +00:00
Chad Rosier 9d51708677 [AArch64] Add support for NEON scalar signed saturating absolute value and
scalar signed saturating negate instructions.

llvm-svn: 192733
2013-10-15 21:18:44 +00:00
Akira Hatanaka 8368b3b3df [mips] Set HI/LO registers' HWEncoding field.
llvm-svn: 192661
2013-10-15 01:00:00 +00:00
Chad Rosier d1f40d760a [AArch64] Add support for NEON scalar integer compare instructions.
llvm-svn: 192596
2013-10-14 14:37:20 +00:00
Bernard Ogden 4400cde89a Add subtarget feature support for Cortex-A53
Some previous implicit defaults have changed, for example FP and NEON
are now on by default.

llvm-svn: 192590
2013-10-14 13:16:57 +00:00
Matheus Almeida 2102188cfc [mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}

llvm-svn: 192589
2013-10-14 13:07:39 +00:00
Matheus Almeida 5be0cd8720 [mips][msa] Direct Object Emission support for VEC instructions.
List of instructions:
and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v.

llvm-svn: 192588
2013-10-14 12:57:18 +00:00
Matheus Almeida 7d65ea76ea [mips][msa] Direct Object Emission of INSVE.{b,h,w,d}.
llvm-svn: 192587
2013-10-14 12:38:17 +00:00
Matheus Almeida bc189eb318 [mips][msa] Direct Object Emission for the majority of the ELM instructions.
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}

llvm-svn: 192586
2013-10-14 12:22:43 +00:00
Matheus Almeida b74293dc55 [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.
INSERT is the first type of MSA instruction that requires a change to the way
MSA registers are parsed. This happens because MSA registers may be suffixed by
an index in the form of an immediate or a general purpose register. The changes
to parseMSARegs reflect that requirement.

llvm-svn: 192582
2013-10-14 11:49:30 +00:00
Craig Topper a422b09ae3 Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.
llvm-svn: 192567
2013-10-14 04:55:01 +00:00
Craig Topper 4432208884 Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.
llvm-svn: 192566
2013-10-14 01:42:32 +00:00
Craig Topper 7158745e55 Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version.
llvm-svn: 192565
2013-10-14 01:21:22 +00:00
Benjamin Kramer 8a37f63714 Mips: Disassemble sign-extended 64 bit immediates properly.
This doesn't change the meaning of the output, but makes look right. PR17539.

llvm-svn: 192483
2013-10-11 19:05:08 +00:00
Amara Emerson ac6950863f [ARM] Fix FP ABI attributes with no VFP enabled.
llvm-svn: 192458
2013-10-11 16:03:43 +00:00
Matheus Almeida 3372c6adb1 This reverts 192447 because of compiler warning generated on darwin build.
llvm-svn: 192451
2013-10-11 13:58:32 +00:00
Matheus Almeida 599446af66 This reverts r192449 because of compiler warning generated on darwin build.
llvm-svn: 192450
2013-10-11 13:56:12 +00:00
Matheus Almeida aa5138b538 [mips][msa] Direct Object Emission for the majority of the ELM instructions.
llvm-svn: 192449
2013-10-11 13:39:49 +00:00
Matheus Almeida 3d0933c425 [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.
INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. 
This happens because MSA registers may be suffixed by an index in the form of an immediate or a
 general purpose register. The changes to parseMSARegs reflect that requirement.

llvm-svn: 192447
2013-10-11 13:29:36 +00:00
Kevin Qin a89e7a0e1c Implement aarch64 neon instruction set AdvSIMD (copy).
llvm-svn: 192410
2013-10-11 02:33:55 +00:00
Hao Liu 99eac7ee44 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 192361
2013-10-10 17:00:52 +00:00
Rafael Espindola 9558af461d Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)."
This reverts commit r192352. It broke the build.

llvm-svn: 192354
2013-10-10 15:15:17 +00:00
Hao Liu 9123ad8ab9 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 192352
2013-10-10 15:01:24 +00:00
Craig Topper 5fb5bd3373 Allow non-AVX form of pmovmskb to take a GR64 operand.
llvm-svn: 192341
2013-10-10 05:33:31 +00:00
Tim Northover 74cf0bd77d AArch64: migrate ADRP relaxation test to be llvm-mc only.
llvm-svn: 192281
2013-10-09 07:53:49 +00:00
Chad Rosier 9849cc6696 [AArch64] Add support for NEON scalar floating-point reciprocal estimate,
reciprocal exponent, and reciprocal square root estimate instructions.

llvm-svn: 192242
2013-10-08 22:09:04 +00:00
Chad Rosier f7ed96ef76 [AArch64] Add support for NEON scalar signed/unsigned integer to floating-point
convert instructions.

llvm-svn: 192231
2013-10-08 20:43:30 +00:00
Craig Topper 72c8cd7bc3 Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse.
llvm-svn: 192171
2013-10-08 05:53:50 +00:00
Amara Emerson 5035ee0212 [ARM] Improve build attributes emission.
llvm-svn: 192111
2013-10-07 16:55:23 +00:00
Chad Rosier b6ceeb9126 [AArch64] Add support for NEON scalar arithmetic instructions:
SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS.

llvm-svn: 192107
2013-10-07 16:36:15 +00:00
Joey Gouly 5aec0598ad [ARMv8] Add some disassembly tests for Thumb sevl/sevl.w
llvm-svn: 192106
2013-10-07 16:13:03 +00:00
Tim Northover f86d1f0b77 ARM: allow cortex-m0 to use hint instructions
The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have
been ported across to the v6M architecture. Fortunately, v6M seems to sit
nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it
fairly easily.

rdar://problem/15144406

llvm-svn: 192097
2013-10-07 11:10:47 +00:00
Craig Topper 07ad1b23bb Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead.
llvm-svn: 192090
2013-10-07 07:19:47 +00:00
Craig Topper a0e0735e6a Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not.
This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior and instruction selection already does this.

llvm-svn: 192088
2013-10-07 05:42:48 +00:00
Craig Topper 2658d89728 Add disassembler support for long encodings for INC/DEC in 32-bit mode.
llvm-svn: 192086
2013-10-07 04:28:06 +00:00
Rafael Espindola ac4ad25a00 Remove some really nasty uses of hasRawTextSupport.
When MC was first added, targets could use hasRawTextSupport to keep features
working before they were added to the MC interface.

The design goal of MC is to provide an uniform api for printing assembly and
object files. Short of relaxations and other corner cases, a object file is
just another representation of the assembly.

It was never the intention that targets would keep doing things like

if (hasRawTextSupport())
  Set flags in one way.
else
  Set flags in another way.

When they do that they create two code paths and the object file is no longer
just another representation of the assembly. This also then requires testing
with llc -filetype=obj, which is extremelly brittle.

This patch removes some of these hacks by replacing them with smaller ones.
The ARM flag setting is trivial, so I just moved it to the constructor. For
Mips, the patch adds two temporary hack directives that allow the assembly
to represent the same things as the object file was already able to.

The hope is that the mips developers will replace the hack directives with
the same ones that gas uses and drop the -print-hack-directives flag.

I will also try to implement a target streamer interface, so that we can
move this out of the common code.

In summary, for any new work, two rules of the thumb are
  * Don't use "llc -filetype=obj" in tests.
  * Don't add calls to hasRawTextSupport.

llvm-svn: 192035
2013-10-05 16:42:21 +00:00
Jiangning Liu ad242fbb71 Implement aarch64 neon instruction set AdvSIMD (Across).
llvm-svn: 192028
2013-10-05 08:22:10 +00:00
Jack Carter 13d5f753f8 reverting per request
llvm-svn: 191992
2013-10-04 22:52:31 +00:00
Jack Carter 721726adfc [MC][AsmParser] Hook for post assembly file processing
This patch handles LLVM standalone assembler (llvm-mc) ELF flag setting based on input file
directive processing.

Mips assembly requires processing inline directives that directly and
indirectly affect the output ELF header flags. This patch handles one
".abicalls".

To process these directives we are following the model the code generator
uses by storing state in a container as we go through processing and when
we detect the end of input file processing, AsmParser is notified and we
update the ELF header flags through a MipsELFStreamer method with a call from
MCTargetAsmParser::emitEndOfAsmFile(MCStreamer &OutStreamer).

This patch will allow other targets the same functionality.

Jack

llvm-svn: 191982
2013-10-04 21:26:15 +00:00
Jiangning Liu ac5fd7e5d3 Implement aarch64 neon instruction set AdvSIMD (3V elem).
llvm-svn: 191944
2013-10-04 09:20:44 +00:00
Amara Emerson 52cfb6a99a [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.
Patch by Artyom Skrobov.

llvm-svn: 191885
2013-10-03 09:31:51 +00:00
Craig Topper 9e3e38ae3f Add XOP disassembler support. Fixes PR13933.
llvm-svn: 191874
2013-10-03 05:17:48 +00:00
Rafael Espindola ae22e3f1ef Add test I forgot to git add in r191824.
llvm-svn: 191831
2013-10-02 14:49:41 +00:00
Richard Sandiford b63e300b67 [SystemZ] Add comparisons of high words and memory
llvm-svn: 191777
2013-10-01 15:00:44 +00:00
Richard Sandiford a9ac0e0f75 [SystemZ] Add comparisons of large immediates using high words
There are no corresponding patterns for small immediates because they would
prevent the use of fused compare-and-branch instructions.

llvm-svn: 191775
2013-10-01 14:56:23 +00:00
Richard Sandiford 42a694f44e [SystemZ] Add immediate addition involving high words
llvm-svn: 191774
2013-10-01 14:53:46 +00:00
Joey Gouly ad98f1671d [ARM] Introduce the 'sevl' instruction in ARMv8.
This also removes the restriction on the immediate field of the 'hint'
instruction.

llvm-svn: 191744
2013-10-01 12:39:11 +00:00
Richard Sandiford 5469c39a26 [SystemZ] Add truncating high-word stores (STCH and STHH)
llvm-svn: 191743
2013-10-01 12:22:49 +00:00
Richard Sandiford 0d46b1a30f [SystemZ] Add zero-extending high-word loads (LLCH and LLHH)
llvm-svn: 191742
2013-10-01 12:19:08 +00:00
Richard Sandiford 89e160d975 [SystemZ] Add sign-extending high-word loads (LBH and LHH)
llvm-svn: 191740
2013-10-01 12:11:47 +00:00
Richard Sandiford a26a4b4f60 [SystemZ] Reapply: Add definitions of LFH and STFH
Originally committed as r191661, but reverted because it changed the matching
order of comparisons on some hosts.  That should have been fixed by r191735.

llvm-svn: 191738
2013-10-01 10:31:04 +00:00
Vladimir Medic 2b953d0b39 This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added.
llvm-svn: 191734
2013-10-01 09:48:56 +00:00
Tilmann Scheller 34b4126769 [ARM] Fix Thumb(-2) diagnostic tests.
Changing the diagnostic message for out of range branch targets in 191686 broke the tests.

The diagnostic message for out of range branch targets was changed to be more consistent with the other diagnostics.
 

llvm-svn: 191691
2013-09-30 18:50:51 +00:00
Jack Carter 8ff70e3e26 [mips][msa] Direct Object Emission for I8 instructions.
This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b.


Patch by Matheus Almeida

llvm-svn: 191688
2013-09-30 18:05:18 +00:00
Jack Carter c3b25686b9 [mips][msa] Direct Object Emission for I5 instructions.
This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.


Patch by Matheus Almeida

llvm-svn: 191687
2013-09-30 17:58:07 +00:00
Jack Carter 92e6e0f171 [mips][msa] Direct Object Emission for 2R instructions.
This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}.  


Patch by Matheus Almeida

llvm-svn: 191685
2013-09-30 17:52:33 +00:00
Jack Carter 6eed9cc6a8 [PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR
and not an MSA register

Patch by Matheus Almeida

llvm-svn: 191684
2013-09-30 17:43:04 +00:00
Tilmann Scheller 0e1dd8c176 [ARM] Use FileCheck instead of grep for ARM LDRD negative tests.
llvm-svn: 191683
2013-09-30 17:31:26 +00:00
Tilmann Scheller 255722beb8 [ARM] Assembler: ARM LDRD with writeback requires the base register to be different from the destination registers.
See ARM ARM A8.8.72.

Violating this constraint results in unpredictable behavior.

llvm-svn: 191678
2013-09-30 16:11:48 +00:00
Tilmann Scheller 38c4ef68d8 [ARM] Assembler: Add more negative tests for ARM LDRD.
llvm-svn: 191664
2013-09-30 13:04:22 +00:00
Richard Sandiford a25f268c25 [SystemZ] Revert r191661: Add definitions of LFH and STFH
For some reason, adding definitions for these load and store
instructions changed whether some of the build bots matched
comparisons as signed or unsigned.

llvm-svn: 191663
2013-09-30 12:01:35 +00:00
Richard Sandiford d30ac3a125 [SystemZ] Add definitions of LFH and STFH
llvm-svn: 191661
2013-09-30 10:50:33 +00:00
Craig Topper 93a3d5973d Add a few more FMA4 disassembler test cases to match the scalar set with regards to combinations of L and W-bits.
llvm-svn: 191650
2013-09-30 02:50:51 +00:00
Craig Topper ed59dd34fd Various x86 disassembler fixes.
Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.

llvm-svn: 191649
2013-09-30 02:46:36 +00:00
Craig Topper c047fe3b5a Revert accidental commit.
llvm-svn: 191633
2013-09-29 08:35:51 +00:00
Craig Topper 3aef88b1c7 Change type of XOP flag in code emitters to a bool. Remove a some unneeded cases from switch.
llvm-svn: 191632
2013-09-29 08:33:34 +00:00
Robert Wilhelm f0cfb83bb4 Fix spelling intruction -> instruction.
llvm-svn: 191610
2013-09-28 11:46:15 +00:00
Yunzhong Gao b8bbcbfcc8 Adding intrinsics to the llvm backend for TBM instruction set.
Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750

llvm-svn: 191539
2013-09-27 18:38:42 +00:00
Tilmann Scheller 1aebfa0a9b ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands.
As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints:

LDRD<c> <Rt>, <Rt2>, ...

(a) Rt must be even-numbered and not r14
(b) Rt2 must be R(t+1)

If those two constraints are not met the result of executing the instruction will be unpredictable.

Constraint (b) was already enforced, this commit adds support for constraint (a).

Fixes rdar://14479793.

llvm-svn: 191520
2013-09-27 13:28:17 +00:00
Tilmann Scheller 88c8f16558 ARM: Teach assembler to enforce constraint for Thumb2 LDRD (literal/immediate) destination register operands.
LDRD<c> <Rt>, <Rt2>, <label>
LDRD<c> <Rt>, <Rt2>, [<Rn>{, #+/-<imm>}]
LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm>
LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]!

As specified in A8.8.72/A8.8.73 in the ARM ARM, the T1 encoding has a constraint which enforces that Rt != Rt2.

If this constraint is not met the result of executing the instruction will be unpredictable.

Fixes rdar://14479780.

llvm-svn: 191504
2013-09-27 10:30:18 +00:00
Yunzhong Gao 4467f33e3c Fixing Intel format of the vshufpd instruction.
Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759

llvm-svn: 191481
2013-09-27 01:44:23 +00:00
Adrian Prantl 6ac40036f1 MCParser/Debug info: Accept line number 0 as a legitimate value, since
CFE produces it to indicate artificial locations.
c.f.: DWARF standard, Table 6.2:
line -- An unsigned integer indicating a source line number. Lines are numbered beginning at 1. The compiler may emit the value 0 in cases where an instruction cannot be attributed to any source line.

llvm-svn: 191471
2013-09-26 23:37:11 +00:00
Jack Carter cb8b40b08d [mips][msa] Direct Object Emission for 3RF instructions.
Patch by Matheus Almeida

llvm-svn: 191461
2013-09-26 21:31:43 +00:00
Venkatraman Govindaraju 3816d43a9a Implements parsing and emitting of .cfi_window_save in MC.
llvm-svn: 191431
2013-09-26 14:49:40 +00:00
David Majnemer 7137420d94 PPC: Allow partial fills in writeNopData()
When asked to pad an irregular number of bytes, we should fill with
zeros.  This is consistent with the behavior specified in the AIX
Assembler Language Reference as well as other LLVM and binutils
assemblers.

N.B. There is a small deviation from binutils' PPC assembler:
when handling pads which are greater than 4 bytes but not mod 4,
binutils will not emit any NOP sequences at all and only use zeros.
This may or may not be a bug but there is no excellent rationale as to
why that behavior is important to emulate.  If that behavior is needed,
we can change writeNopData() to behave in the same way.

This fixes PR17352.

llvm-svn: 191426
2013-09-26 09:18:48 +00:00
David Majnemer 6ad26d3364 PPC: Add support for fctid and fctiw
Encodings were checked against the Power ISA documents and double
checked against binutils.

This fixes PR17350.

llvm-svn: 191419
2013-09-26 04:11:24 +00:00
Jack Carter 3eb663b037 [mips][msa] Direct Object Emission for 3R instructions.
This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class.
 
Patch by Matheus Almeida

llvm-svn: 191415
2013-09-26 00:09:46 +00:00
Jack Carter 3381298227 [mips][msa] Direct Object Emission for 2RF instructions.
Patch by Matheus Almeida

llvm-svn: 191413
2013-09-25 23:56:25 +00:00
Jack Carter 5dc8ac92b9 [mips][msa] Direct Object Emission support for the MSA instruction set.
In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions.

Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function).

Patch by Matheus Almeida

llvm-svn: 191412
2013-09-25 23:50:44 +00:00
David Majnemer 0c58bc64a4 MC: Add support for treating $ as a reference to the PC
The binutils assembler supports a mode called DOLLAR_DOT which treats
the dollar sign token as a reference to the current program counter if
the dollar sign doesn't precede a constant or identifier.

This commit adds a new MCAsmInfo flag stating whether or not a given
target supports this interpretation of the dollar sign token; by
default, this flag is not enabled.

Further, enable this flag for PPC. The system assembler for AIX and
binutils both support using the dollar sign in this manner.

This fixes PR17353.

llvm-svn: 191368
2013-09-25 10:47:21 +00:00
Roman Divacky e33098f5cb Make the size and expr arguments of .fill directive optional.
llvm-svn: 191318
2013-09-24 17:44:41 +00:00
Jiangning Liu 63dc840fc5 Initial support for Neon scalar instructions.
Patch by Ana Pazos.

1.Added support for v1ix and v1fx types.
2.Added Scalar Pairwise Reduce instructions.
3.Added initial implementation of Scalar Arithmetic instructions.

llvm-svn: 191263
2013-09-24 02:47:27 +00:00
David Majnemer 7b1cdb980b X86: Use R_X86_64_TPOFF64 for FK_Data_8
Summary:
LLVM would crash when trying to come up with a relocation type for
assembly like:
movabsq $V@TPOFF, %rax

Instead, we say the relocation type is R_X86_64_TPOFF64.

Fixes PR17274.

Reviewers: dblaikie, nrieck, rafael

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1717

llvm-svn: 191163
2013-09-22 05:30:16 +00:00
David Majnemer f90c3b5a1c ELF: Parse types in directives like binutils gas
Allow binutils .type and .section directives to take the following
forms:
- @<type>
- %<type>
- "<type>"

llvm-svn: 191134
2013-09-21 05:25:12 +00:00
Amara Emerson 3308909508 [ARMv8] Add support for the v8 cryptography extensions.
llvm-svn: 190996
2013-09-19 11:59:01 +00:00
Richard Sandiford 93183ee78c [SystemZ] Add unsigned compare-and-branch instructions
For some reason I never got around to adding these at the same time as
the signed versions.  No idea why.

I'm not sure whether this SystemZII::BranchC* stuff is useful, or whether
it should just be replaced with an "is normal" flag.  I'll leave that
for later though.

There are some boundary conditions that can be tweaked, such as preferring
unsigned comparisons for equality with [128, 256), and "<= 255" over "< 256",
but again I'll leave those for a separate patch.

llvm-svn: 190930
2013-09-18 09:56:40 +00:00
Joey Gouly 36b2e5de3c 'svn add' the test cases.
llvm-svn: 190929
2013-09-18 09:46:49 +00:00
Reid Kleckner c1e7621e01 COFF: Ensure that objects produced by LLVM link with /safeseh
Summary:
We indicate that the object files are safe by emitting a @feat.00
absolute address symbol.  The address is presumably interpreted as a
bitfield of features that the compiler would like to enable.  Bit 0 is
documented in the PE COFF spec to opt in to "registered SEH", which is
what /safeseh enables.

LLVM's object files are safe by default because LLVM doesn't know how to
produce SEH handlers.

Reviewers: Bigcheese

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1691

llvm-svn: 190898
2013-09-17 23:18:05 +00:00
Reid Kleckner 3ea536fef4 COFF: Emit all MCSymbols rather than filtering out some of them
In particular, this means we emit non-external symbols defined to
variables, such as aliases or absolute addresses.

This is needed to implement /safeseh, and it appears there was some
confusion about what symbols to emit previously.

llvm-svn: 190888
2013-09-17 21:24:44 +00:00
Joey Gouly 830c27ab2d [ARM] Fix the deprecation of MCR encodings that map to CP15{ISB,DSB,DMB}.
llvm-svn: 190862
2013-09-17 09:54:57 +00:00
Kevin Qin 36399e6b68 Implement 3 AArch64 neon instructions : umov smov ins.
llvm-svn: 190839
2013-09-17 02:21:02 +00:00
Vladimir Medic 05bcde6d9a This patch implements Mips load/store instructions from/to coprocessor 2. Test cases are added.
llvm-svn: 190780
2013-09-16 10:29:42 +00:00
Benjamin Kramer ac511cac77 ELF: Add support for the exclude section bit for gas compat.
llvm-svn: 190769
2013-09-15 19:53:20 +00:00
David Majnemer a4b521b7fc MC: Add support for '?' flags in .section directives
Summary:
The '?' flag uses the last section group if the last had a section
group.  We treat combining an explicit section group and the '?' as a
hard error.

This fixes PR17198.

Reviewers: rafael, bkramer

Reviewed By: bkramer

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1686

llvm-svn: 190768
2013-09-15 19:24:16 +00:00
Kai Nacke 8539b4637b Fix alignment of unwind data.
For alignment purposes, the instruction array will always have an even
number of entries, with the final entry potentially unused (in which
case the array will be one longer than indicated by the count of unwind
codes field).

Reviewed by Anton Korobeynikov, Charles Davis and Nico Rieck.

llvm-svn: 190767
2013-09-15 18:01:09 +00:00
Kai Nacke 74adc8a457 Generate IMAGE_REL_AMD64_ADDR32NB relocations for SEH
data structures.

The Win64 EH data structures must be of type IMAGE_REL_AMD64_ADDR32NB
instead of IMAGE_REL_AMD64_ADDR32. This is easiely achieved by adding
the VK_COFF_IMGREL32 modifier to the symbol reference.
Change also references to start and end of the SEH range of a function
as offsets to start of the function.

Reviewed by Jim Grosbach, Charles Davis and Nico Rieck.

llvm-svn: 190766
2013-09-15 17:46:46 +00:00
Ben Langmuir 8eb45a4ef6 Add the remaining Intel SHA instructions
Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit
xmm0 dependency.

llvm-svn: 190754
2013-09-14 15:03:21 +00:00
Zoran Jovanovic fc26cfcde7 Fixed bug when generating Load Upper Immediate microMIPS instruction.
llvm-svn: 190746
2013-09-14 07:35:41 +00:00
Zoran Jovanovic 3671a5441a Support for microMIPS DIV instructions.
llvm-svn: 190745
2013-09-14 07:15:21 +00:00
Zoran Jovanovic ab85278137 Support for misc microMIPS instructions.
llvm-svn: 190744
2013-09-14 06:49:25 +00:00
Amaury de la Vieuville 9867f8649b Fix tests for hasFPARMv8 name change (r190692)
Patch by Bradley Smith

llvm-svn: 190694
2013-09-13 14:37:52 +00:00
Joey Gouly ccd04894c4 [ARMv8] Change hasV8Fp to hasFPARMv8, and other command line options
to be more consistent.

llvm-svn: 190692
2013-09-13 13:46:57 +00:00
Tim Northover 635a979038 AArch64: use RegisterOperand for NEON registers.
Previously we modelled VPR128 and VPR64 as essentially identical
register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias"
sub-registers). This model is starting to cause significant problems
for code generation, particularly writing EXTRACT/INSERT_SUBREG
patterns for converting between the two.

The change here switches to classifying VPR64 & VPR128 as
RegisterOperands, which are essentially aliases for RegisterClasses
with different parsing and printing behaviour. This fits almost
exactly with their real status (VPR128 == FPR128 printed strangely,
VPR64 == FPR64 printed strangely).

llvm-svn: 190665
2013-09-13 07:26:52 +00:00
Roman Divacky 62cb63543b Implement asm support for a few PowerPC bookIII that are needed for assembling
FreeBSD kernel.

llvm-svn: 190618
2013-09-12 17:50:54 +00:00
Ben Langmuir 1650175de6 Partial support for Intel SHA Extensions (sha1rnds4)
Add basic assembly/disassembly support for the first Intel SHA
instruction 'sha1rnds4'. Also includes feature flag, and test cases.

Support for the remaining instructions will follow in a separate patch.

llvm-svn: 190611
2013-09-12 15:51:31 +00:00
Hal Finkel 0096dbd50d Mark PPC MFTB and DST (and friends) as deprecated
Use the new instruction deprecation feature to mark mftb (now replaced with
mfspr) and dst (along with the other Altivec cache control instructions) as
deprecated when targeting cores supporting at least ISA v2.03.

llvm-svn: 190605
2013-09-12 14:40:06 +00:00
Joey Gouly 904d8806ce Somehow this important part of the patch, where I actually check the Mask,
got lost during my iterations of review.

Thanks to Hal for spotting it!

llvm-svn: 190604
2013-09-12 14:23:19 +00:00
Joey Gouly 0e76fa7df5 Add an instruction deprecation feature to TableGen.
The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.

The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
  ComplexDeprecationPredicate<"MCR">

would mean you would have to define the following function:
  bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
                             std::string &Info)

Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.

The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.

llvm-svn: 190598
2013-09-12 10:28:05 +00:00
Elena Demikhovsky 8952974e29 AVX-512: implemented extractelement with variable index.
Added parsing of mask register and "zeroing" semantic, like {%k1} {z}.

llvm-svn: 190595
2013-09-12 08:55:00 +00:00
Richard Sandiford a9eb9972e4 [SystemZ] Add TM and TMY
The main complication here is that TM and TMY (the memory forms) set
CC differently from the register forms.  When the tested bits contain
some 0s and some 1s, the register forms set CC to 1 or 2 based on the
value the uppermost bit.  The memory forms instead set CC to 1
regardless of the uppermost bit.

Until now, I've tried to make it so that a branch never tests for an
impossible CC value.  E.g. NR only sets CC to 0 or 1, so branches on the
result will only test for 0 or 1.  Originally I'd tried to do the same
thing for TM and TMY by using custom matching code in ISelDAGToDAG.
That ended up being very ugly though, and would have meant duplicating
some of the chain checks that the common isel code does.

I've therefore gone for the simpler alternative of adding an extra
operand to the TM DAG opcode to say whether a memory form would be OK.
This means that the inverse of a "TM;JE" is "TM;JNE" rather than the
more precise "TM;JNLE", just like the inverse of "TMLL;JE" is "TMLL;JNE".
I suppose that's arguably less confusing though...

llvm-svn: 190400
2013-09-10 10:20:32 +00:00
Vladimir Medic 65cd57445e Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of register when PFU is 32 bit.
llvm-svn: 190397
2013-09-10 09:50:01 +00:00
Jiangning Liu 2878dc8fe7 Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions,
SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL

llvm-svn: 190288
2013-09-09 02:20:27 +00:00
Akira Hatanaka 6a3fe57444 [mips] Add definition of instruction "drotr32" (double rotate right plus 32).
llvm-svn: 190232
2013-09-07 00:18:01 +00:00
Akira Hatanaka dffc542123 [mips] Set instruction itineraries of loads, stores and conditional moves.
llvm-svn: 190219
2013-09-06 23:28:24 +00:00
Vladimir Medic b936da159e This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
llvm-svn: 190154
2013-09-06 13:08:00 +00:00
Vladimir Medic 457ba56b05 This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
llvm-svn: 190152
2013-09-06 12:53:21 +00:00
Vladimir Medic e0fbb44a48 This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
llvm-svn: 190148
2013-09-06 12:41:17 +00:00
Vladimir Medic dde3d582a2 This patch adds support for microMIPS disassembler and disassembler make check tests.
llvm-svn: 190144
2013-09-06 12:30:36 +00:00
Kevin Enderby 09cdb4385f Fixed a crash in the integrated assembler for Mach-O when a symbol difference
expression uses an assembler temporary symbol from an assignment.  In this case
the symbol does not have a fragment so the use of getFragment() would be NULL
and caused a crash. In the case of an assembler temporary symbol we want to use
the AliasedSymbol (if any) which will create a local relocation entry, but if
it is not an assembler temporary symbol then let it use that symbol with an
external relocation entry.

rdar://9356266

llvm-svn: 190096
2013-09-05 20:25:06 +00:00
Yunzhong Gao 8c0f5067cc Improve handling of .file, .include and .incbin directives to
allow escaped octal character sequences.

The patch was discussed in Phabricator. See:
http://llvm-reviews.chandlerc.com/D1289

llvm-svn: 190089
2013-09-05 19:14:26 +00:00
Joey Gouly c209d6aa3e [ARMv8] Add some missing tests for DSB/DMB.
llvm-svn: 190060
2013-09-05 16:05:45 +00:00
Joey Gouly 926d3f5809 [ARMv8] Implement the new DMB/DSB operands.
This removes the custom ISD Node: MEMBARRIER and replaces it
with an intrinsic.

llvm-svn: 190055
2013-09-05 15:35:24 +00:00
Richard Barton 8d519fe015 Add AArch32 DCPS{1,2,3} and HLT instructions.
These were pretty straightforward instructions, with some assembly support
required for HLT.

The ARM assembler is keen to split the instruction mnemonic into a
(non-existent) 'H' instruction with the LT condition code. An exception for
HLT is needed.

HLT follows the same rules as BKPT when in IT blocks, so the special BKPT
hadling code has been adapted to handle HLT also.

Regression tests added including diagnostic tests for out of range immediates
and illegal condition codes, as well as negative tests for pre-ARMv8.

llvm-svn: 190053
2013-09-05 14:14:19 +00:00
Richard Sandiford 178273a174 [SystemZ] Add NC, OC and XC
For now these are just used to handle scalar ANDs, ORs and XORs in which
all operands are memory.

llvm-svn: 190041
2013-09-05 10:36:45 +00:00
Hao Liu d4aede098f Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:
sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll
 and 4 convert instructions:
      scvtf,ucvtf,fcvtzs,fcvtzu

llvm-svn: 189925
2013-09-04 09:28:24 +00:00
Richard Mitton 576ee003d0 Fixed a bug where diassembling an instruction that had a prefix would cause LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode.
llvm-svn: 189698
2013-08-30 21:19:48 +00:00
Kevin Enderby 74946758a0 The darwin integrated assembler for X86 in 64-bit mode is not rejecting
32-bit absolute addressing in instructions likei this:

	mov $_f, %rsi

which is not supported in 64-bit mode.

rdar://8827134

llvm-svn: 189543
2013-08-29 00:19:03 +00:00
Kevin Enderby 3aeada287b The integrated darwin assembler can hang in an infinite loop (or get an assert
with a debug build) with this buggy .indirect_symbol directive usage:

% cat test.s
x: .indirect_symbol _y

The assertion is because it is trying to get the symbol index for the
symbol _y when it is writing out the indirect symbol table. This line of
code in MachObjectWriter::WriteObject() :

        Write32(Asm.getSymbolData(*it->Symbol).getIndex());

And while there is a symbol _y it does not have any getSymbolData set which
is only done in MachObjectWriter::BindIndirectSymbols() for pointer sections
or stub sections.  I added a check and an error in there to catch this in case
something slips through.

But to get a better error the parser should detect when a .indirect_symbol
directive is used and it is not in a pointer section or stub section.  To make
that work I moved the handling of the indirect symbol out of the target
independent AsmParser code into the DarwinAsmParser code that can check
for the proper Mach-O section types.

rdar://14825505

llvm-svn: 189497
2013-08-28 17:50:59 +00:00
Joey Gouly daf0e378d2 [ARMv8]
Fix a few things in one swoop.

# Add some negative tests.
# Fix some formatting issues.
# Add some missing IsThumb / ARMv8
# Fix some outs / ins mistakes.

llvm-svn: 189490
2013-08-28 16:39:20 +00:00
Richard Sandiford 35b9be298a [SystemZ] Add support for TMHH, TMHL, TMLH and TMLL
For now just handles simple comparisons of an ANDed value with zero.
The CC value provides enough information to do any comparison for a
2-bit mask, and some nonzero comparisons with more populated masks,
but that's all future work.

llvm-svn: 189469
2013-08-28 10:31:43 +00:00
Akira Hatanaka 9bfa2e2e7f [mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
Also, fix predicates.

llvm-svn: 189432
2013-08-28 00:55:15 +00:00
David Majnemer aa34d79ab5 [ms-inline asm] Support offsets after segment registers
Summary: MASM let's you do stuff like 'MOV FS:20, EAX' and 'MOV EAX, FS:20'

Reviewers: craig.topper, rnk

Reviewed By: rnk

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1470

llvm-svn: 189407
2013-08-27 21:56:17 +00:00
Joerg Sonnenberger b822af4721 Given target assembler parsers a chance to handle variant expressions
first. Use this to turn the PPC modifiers into PPC specific expressions,
allowing them to work on constants.

llvm-svn: 189400
2013-08-27 20:23:19 +00:00
Joey Gouly e6d165ccb4 [ARMv8] Add MC support for the new load/store acquire/release instructions.
llvm-svn: 189388
2013-08-27 17:38:16 +00:00
Joey Gouly a710d810f5 [ARMv8] Add some negative tests for the recent VFP/NEON instructions.
Fix two issues I found while writing these tests.

llvm-svn: 189341
2013-08-27 11:24:16 +00:00
Kai Nacke 1b7e4866f4 Fix wrong code offset for unwind code SET_FPREG.
The code offset for unwind code SET_FPREG is wrong because it is set
to constant 0. The fix is to do the same as for the other unwind
codes: emit a label and later the absolute difference between the
label and the begin of the prologue.
Also enables the failing test case MC/COFF/seh.s

Reviewed by Jim Grosbach, Charles Davis and Nico Rieck.

llvm-svn: 189309
2013-08-27 04:16:16 +00:00
Vladimir Medic 8277c1874a This patch implements trap instructions for mips. The test cases are added.
llvm-svn: 189213
2013-08-26 10:02:40 +00:00
Craig Topper 1885417372 First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions.
-Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted.
-x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size.
-Intel syntax printing prints the ptr size and places brackets around the address immediate.

Known remaining issues with these instructions:
-Segment override prefix is not supported. PR16962 and PR16961.
-Immediate size should be changed by address size prefix.

llvm-svn: 189201
2013-08-25 22:23:38 +00:00
Richard Sandiford 03481334b5 [SystemZ] Add basic prefetch support
Just the instructions and intrinsics for now.

llvm-svn: 189100
2013-08-23 11:36:42 +00:00
Mihai Popa 5500c0ff89 Fix ARM vcvt encoding when the number of fractional bits is zero.
The instruction to convert between floating point and fixed point representations
takes an immediate operand for the number of fractional bits of the fixed point
value. ARMARM specifies that when that number of bits is zero, the assembler
should encode floating point/integer conversion instructions. 

This patch adds the necessary instruction aliases to achieve this behaviour.

llvm-svn: 189009
2013-08-22 13:16:07 +00:00
Mihai Popa ae1112bae5 Make "mov" work for all Thumb2 MOV encodings
According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings.
To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV.

llvm-svn: 188901
2013-08-21 13:14:58 +00:00
Elena Demikhovsky 33d447a2d6 AVX-512: Added SHIFT instructions.
llvm-svn: 188899
2013-08-21 09:36:02 +00:00
Richard Sandiford 8e92c389e4 [SystemZ] Add FI[EDX]BRA
These are extensions of the existing FI[EDX]BR instructions, but use a spare
bit to suppress inexact conditions.

llvm-svn: 188894
2013-08-21 08:58:08 +00:00
Akira Hatanaka 39f915b58a [micromips] Print instruction alias "not" if the last operand of a nor is zero.
llvm-svn: 188851
2013-08-21 01:18:46 +00:00
Akira Hatanaka a43b56d9af [mips] Guard micromips instructions with predicate InMicroMips. Also, fix
assembler predicate HasStdEnd so that it is false when the target is micromips.

llvm-svn: 188824
2013-08-20 20:46:51 +00:00
Akira Hatanaka ff7beb1754 [mips] Fix instruction definitions that were incorrectly marked as code-gen-only.
llvm-svn: 188690
2013-08-19 19:08:03 +00:00
Mihai Popa 4a9df8a768 Thumb2 add immediate alias for SP
The Thumb2 add immediate is in fact defined for SP. The manual is misleading as it points to a different section for add immediate with SP, however the encoding is the same as for add immediate with register only with the SP operand hard coded. As such add immediate with SP and add immediate with register can safely be treated as the same instruction.

All the patch does is adjust a register constraint on an instruction alias.

llvm-svn: 188676
2013-08-19 15:02:25 +00:00
Richard Sandiford 784a580312 [SystemZ] Add negative integer absolute (load negative)
For now this matches the equivalent of (neg (abs ...)), which did hit a few
times in projects/test-suite.  We should probably also match cases where
absolute-like selects are used with reversed arguments.

llvm-svn: 188671
2013-08-19 12:56:58 +00:00
Richard Sandiford 4b89705490 [SystemZ] Add integer absolute (load positive)
llvm-svn: 188670
2013-08-19 12:48:54 +00:00
Hal Finkel dbc78e1f73 Add the PPC fcpsgn instruction
Modern PPC cores support a floating-point copysign instruction, and we can use
this to lower the FCOPYSIGN node (which is created from calls to the libm
copysign function). A couple of extra patterns are necessary because the
operand types of FCOPYSIGN need not agree.

llvm-svn: 188653
2013-08-19 05:01:02 +00:00
Mihai Popa 46c1bcb4e9 Add support for Thumb2 literal loads with negative zero offset
Thumb2 literal loads use an offset encoding which allows for 
negative zero. This fixes parsing and encoding so that #-0 
is correctly processed. The parser represents #-0 as INT32_MIN.

llvm-svn: 188549
2013-08-16 12:03:00 +00:00
Mihai Popa cf276b2c88 Fix Thumb2 aliasing complementary instructions taking modified immediates
There are many Thumb instructions which take 12-bit immediates encoded in a special
8-byte value + 4-byte rotator form. Not all numbers are represented, and it's legal
to transform an assembly instruction to be able to encode the immediate.

For example: AND and BIC are complementary instructions; one can switch the AND
to a BIC as long as the immediate is complemented. 

The intent is to switch one instruction into its complementary one when the immediate
cannot be encoded in the form requested in the original assembly and when the 
complementary immediate is encodable.

The patch addresses two issues:
1. definition of t2SOImmNot immediate - it has to check that the orignal value is
not encoded naturally
2. t2AND and t2BIC instruction aliases which should use the Thumb2 SOImm operand 
rather than the ARM one.

llvm-svn: 188548
2013-08-16 11:55:44 +00:00
Richard Sandiford 0dec06a28c [SystemZ] Use SRST to implement strlen and strnlen
It would also make sense to use it for memchr; I'm working on that now.

llvm-svn: 188547
2013-08-16 11:41:43 +00:00
Richard Sandiford bb83a50f57 [SystemZ] Use MVST to implement strcpy and stpcpy
llvm-svn: 188546
2013-08-16 11:29:37 +00:00
Richard Sandiford ca23271010 [SystemZ] Use CLST to implement strcmp
llvm-svn: 188544
2013-08-16 11:21:54 +00:00
Vladimir Medic 2df9ee6ec8 This patch implements wait instruction for mips. Examples are added in test files.
llvm-svn: 188537
2013-08-16 10:17:03 +00:00
Daniel Dunbar 9efbedfd35 [tests] Cleanup initialization of test suffixes.
- Instead of setting the suffixes in a bunch of places, just set one master
   list in the top-level config. We now only modify the suffix list in a few
   suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py).

 - Aside from removing the need for a bunch of lit.local.cfg files, this enables
   4 tests that were inadvertently being skipped (one in
   Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and
   CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been
   XFAILED).

 - This commit also fixes a bunch of config files to use config.root instead of
   older copy-pasted code.

llvm-svn: 188513
2013-08-16 00:37:11 +00:00
Mihai Popa d79f00ba68 This fixes three issues related to Thumb literal loads:
1. The offset range for Thumb1 PC relative loads is [0..1020] and not [-1024..1020]
2. Thumb2 PC relative loads may define the PC, so the restriction placed on target register is removed
3. Removes unneeded alias between "ldr.n" and t1LDRpci. ".n" is actually stripped by both tablegen
and the ASM parser, so this alias rule really does nothing

llvm-svn: 188466
2013-08-15 15:43:06 +00:00
Hao Liu cd8b02dce3 Clang and AArch64 backend patches to support shll/shl and vmovl instructions and ACLE functions
llvm-svn: 188451
2013-08-15 08:26:11 +00:00
Tim Northover 680c1acc84 Add test-case for hex floating-literals
Somehow I forgot to test one of the error conditions I'd added.

llvm-svn: 188372
2013-08-14 14:55:54 +00:00
Tim Northover 1f25623449 Support C99 hexadecimal floating-point literals in assembly
It's useful to be able to write down floating-point numbers without having to
worry about what they'll be rounded to (as C99 discovered), this extends that
ability to the MC assembly parsers.

llvm-svn: 188370
2013-08-14 14:23:31 +00:00
Akira Hatanaka 274d24c8bc [mips] Fix bug in parsing accumulator registers.
llvm-svn: 188344
2013-08-14 01:15:52 +00:00
Jack Carter 9770097727 [Mips] Support for unaligned load/store microMips instructions
This includes instructions lwl, lwr, swl and swr.

Patch by Zoran Jovnovic

llvm-svn: 188312
2013-08-13 20:19:16 +00:00
Joey Gouly 9960e764aa ARMv8: SWP and SWPB are obsoleted on ARMv8.
llvm-svn: 188288
2013-08-13 16:40:47 +00:00
Mihai Popa 0e1012f0f4 Fix signed overflow in when computing encodings for ADR instructions
llvm-svn: 188268
2013-08-13 14:02:13 +00:00
David Majnemer 3d96acb735 [-cxx-abi microsoft] Stick zero initialized symbols into the .bss section for COFF
Summary:
We need to do two things:

- Initialize BSSSection in MCObjectFileInfo::InitCOFFMCObjectFileInfo
- Teach TargetLoweringObjectFileCOFF::SelectSectionForGlobal what to do
  with it

This fixes PR16861.

Reviewers: rnk

Reviewed By: rnk

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1361

llvm-svn: 188244
2013-08-13 01:23:53 +00:00
Kevin Enderby b03f3fe4e8 Fix a crash with X86 Mach-O and a subtraction expression where both symbols are
undefined and produce an error message instead as this is a non-relocatable
expression with X86 Mach-O.

rdar://8920876

llvm-svn: 188218
2013-08-12 22:45:44 +00:00
Vladimir Medic 939877ee14 This patch implements ei and di instructions for mips. Test cases are added.
llvm-svn: 188176
2013-08-12 13:07:23 +00:00
Tim Northover 501977eb7a Fix FileCheck --check-prefix lines.
Various tests had sprung up over the years which had --check-prefix=ABC on the
RUN line, but "CHECK-ABC:" later on. This happened to work before, but was
strictly incorrect. FileCheck is getting stricter soon though.

Patch by Ron Ofir.

llvm-svn: 188173
2013-08-12 12:43:26 +00:00
Richard Sandiford 761703a248 [SystemZ] Add a definition of the CLC instruction
llvm-svn: 188162
2013-08-12 10:17:33 +00:00
Richard Sandiford 87326c73c6 [SystemZ] Add a definition of the IPM instruction
llvm-svn: 188161
2013-08-12 10:05:58 +00:00
Rafael Espindola 6ee163875c Check for $PWD in llvm::sys::current_path.
Some users (clang, libTooling) require this. After this patch we can remove
the calls to getenv("PWD") from clang.

llvm-svn: 188125
2013-08-10 00:50:57 +00:00
Mihai Popa 4c2801f7fd This fixes the Thumb2 CPS assembly syntax.
In Thumb1, only one variant is supported: CPS{effect} {flags}

Thumb2 supports three:
CPS{effect}.W {flags}
CPS{effect} {flags} {mode}
CPS {mode}

Canonically, .W should be used only when ambiguity is present between encodings of different width.
The wide suffix is still accepted for the latter two forms via aliases.

llvm-svn: 188071
2013-08-09 13:52:32 +00:00
Mihai Popa ad18d3ce53 Fix assembling of Thumb2 branch instructions.
The long encoding for Thumb2 unconditional branches is broken.
Additionally, there is no range checking for target operands; as such 
for instructions originating in assembly code, only short Thumb encodings
are generated, regardless of the bitsize needed for the offset.

Adding range checking is non trivial due to the representation of Thumb
branch instructions. There is no true difference between conditional and
unconditional branches in terms of operands and syntax - even unconditional
branches have a predicate which is expected to match that of the IT block
they are in. Yet, the encodings and the permitted size of the offset differ.

Due to this, for any mnemonic there are really 4 encodings to choose for.

The problem cannot be handled in the parser alone or by manipulating td files.
Because the parser builds first a set of match candidates and then checks them
one by one, whatever tablegen-only solution might be found will ultimately be
dependent of the parser's evaluation order. What's worse is that due to the fact
that all branches have the same syntax and the same kinds of operands, that 
order is governed by the lexicographical ordering of the names of operand 
classes...

To circumvent all this, any necessary disambiguation is added to the instruction
validation pass.

llvm-svn: 188067
2013-08-09 10:38:32 +00:00
Jack Carter 7bd3c7d1fc Mips ELF: MicroMips direct object Little endian support.
Test included.

Patch by Zoran Jovanovich

llvm-svn: 188024
2013-08-08 23:30:40 +00:00
David Majnemer f76d6b3712 Revert "coff also doesn't have a ReadOnlySection yet, (!)"
This reverts commit r77814.

We were sticking global constants in the .data section instead of in the
.rdata section when emitting for COFF.

This fixes PR16831.

llvm-svn: 187956
2013-08-08 01:50:52 +00:00
Eric Christopher 7af8baf678 Using the integrated assembler we'd fail to change section to the
.tbss section for zerofill thread locals. Make sure we do this
before emitting the zerofills.

Fixes PR15972.

llvm-svn: 187913
2013-08-07 21:13:06 +00:00
Richard Sandiford 9f11bc1956 [SystemZ] Add floating-point load-and-test instructions
These instructions can also be used as comparisons with zero.

llvm-svn: 187882
2013-08-07 11:03:34 +00:00
Mihai Popa c34bf73ebb This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci,
as pldw does not have a literal variant (i.e. pc relative version)

llvm-svn: 187804
2013-08-06 16:07:46 +00:00
Mihai Popa 8f49a45c68 Support APSR_nzcv as operand for Thumb2 mrc. Deprecate pre-UAL syntax (pc instead of apsr_nzcv)
llvm-svn: 187803
2013-08-06 15:52:36 +00:00
Richard Sandiford 9795d8e611 [SystemZ] Add definitions for BRCT and BRCTG
llvm-svn: 187721
2013-08-05 11:07:38 +00:00
Richard Sandiford c62c64a038 [SystemZ] Add LOAD AND TEST instructions
Just the definitions and MC support.  The next patch uses them for codegen.

llvm-svn: 187719
2013-08-05 11:00:53 +00:00
Joey Gouly 5d0564d2e6 [ARMv8] Add an assembler warning for the deprecated 'setend' instruction.
llvm-svn: 187666
2013-08-02 19:18:12 +00:00
Elena Demikhovsky b1266b5447 EVEX and compressed displacement encoding for AVX512
llvm-svn: 187576
2013-08-01 13:34:06 +00:00
Vladimir Medic deaa618cdc Add tests for Mips DSP instructions.
llvm-svn: 187570
2013-08-01 09:35:25 +00:00
Tim Northover 40e9efd725 AArch64: add initial NEON support
Patch by Ana Pazos.

- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise

- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic

- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same

- Intial implementation of instruction class:
Scalar Arithmetic

- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.

- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.

llvm-svn: 187567
2013-08-01 09:20:35 +00:00
Kevin Enderby 78f9572f39 Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
While the .td entry is nice and all, it takes a pretty gross hack in
ARMAsmParser::ParseInstruction() because of handling of other "subs"
instructions to get it to match.  Ran it by Jim Grosbach and he said it was
about what he expected to make this work given the existing code.

rdar://14214063

llvm-svn: 187530
2013-07-31 21:05:30 +00:00
Richard Sandiford 6cf80b3ec0 [SystemZ] Add RISBLG and RISBHG instruction definitions
The next patch will make use of RISBLG for codegen.

llvm-svn: 187490
2013-07-31 11:17:35 +00:00
Craig Topper efd67d4612 Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax.
Patch by Richard Mitton.

llvm-svn: 187476
2013-07-31 02:47:52 +00:00
Vladimir Medic 643b398786 This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
llvm-svn: 187410
2013-07-30 10:12:14 +00:00
Nico Rieck 7fdaee8f15 Use proper section suffix for COFF weak symbols
32-bit symbols have "_" as global prefix, but when forming the name of
COMDAT sections this prefix is ignored. The current behavior assumes that
this prefix is always present which is not the case for 64-bit and names
are truncated.

llvm-svn: 187356
2013-07-29 13:58:39 +00:00
Nico Rieck 2c9c89b21d MC: Support larger COFF string tables
Single-slash encoded entries do not require a terminating null. This bumps
the maximum table size from ~1MB to ~9.5MB.

llvm-svn: 187352
2013-07-29 12:30:12 +00:00
Akira Hatanaka 8bce21c154 [mips] Fix FP conditional move instructions to have explicit FP condition code
register operands.

llvm-svn: 187242
2013-07-26 20:51:20 +00:00
Akira Hatanaka 1fb1b8b811 [mips] Fix FP branch instructions to have explicit FP condition code register
operands.

llvm-svn: 187238
2013-07-26 20:13:47 +00:00
Akira Hatanaka 53900e5124 [mips] Print instructions "beq", "bne" and "or" using assembler pseudo
instructions "beqz", "bnez" and "move", when possible.

beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or  $2, $3, $zero  => move $2, $3

llvm-svn: 187229
2013-07-26 18:34:25 +00:00
Craig Topper a7316c2e64 Add test cases for the various instruction alias and Intel syntax fixes that have gone in lately.
llvm-svn: 187188
2013-07-26 05:39:33 +00:00
Rafael Espindola 729866670b Remove the mblaze backend from llvm.
Approval in here http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-July/064169.html

llvm-svn: 187145
2013-07-25 18:55:05 +00:00
Richard Sandiford f2404164ba [SystemZ] Add LOCR and LOCGR
llvm-svn: 187113
2013-07-25 09:11:15 +00:00
Richard Sandiford 09a8cf3604 [SystemZ] Add LOC and LOCG
As with the stores, these instructions can trap when the condition is false,
so they are only used for things like (cond ? x : *ptr).

llvm-svn: 187112
2013-07-25 09:04:52 +00:00
Richard Sandiford a68e6f5660 [SystemZ] Add STOC and STOCG
These instructions are allowed to trap even if the condition is false,
so for now they are only used for "*ptr = (cond ? x : *ptr)"-style
constructs.

llvm-svn: 187111
2013-07-25 08:57:02 +00:00
Rafael Espindola 91997c0f94 Add not so that these tests pass with pipefail enabled.
llvm-svn: 186939
2013-07-23 13:18:20 +00:00
Craig Topper db90f65bbe Don't let x86 asm printer use the no operand movsd alias. It should use the normal movsl instead.
llvm-svn: 186924
2013-07-23 01:50:47 +00:00
Kevin Enderby 285da02094 Fix the move to/from accumulator register instructions that use a full 64-bit
absolute address encoded in the instruction.

rdar://8612627 and rdar://14299221

llvm-svn: 186878
2013-07-22 21:25:31 +00:00
Craig Topper 998bcf9534 Recommit r186813: More Intel syntax alias fixes. With the addition of suppressing some of the aliases from being emitted by the asm printer.
llvm-svn: 186869
2013-07-22 20:46:37 +00:00